Lecture Notes in Electrical Engineering

By: Srinivasan Murali

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Hardcover | 21 April 2009

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212 Pages

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Preface. 1 Introduction. 1.1 Networks on Chips: Scalable interconnects for SoCs. 1.2 NoC Design Challenges. 1.3 Book Overview. 1.4 Related Work. Part I NoC Design Methods 2 Designing Crossbar Based Systems. 2.1 Problem Motivation and Application Traffic Analysis. 2.2 Design Methodology. 2.3 Exact Approach to Crossbar Synthesis. 2.4 Heuristic Approach to Crossbar Synthesis. 2.5 Experiments and Case Studies. 2.6 Summary. 3 Netchip Tool Flow For NoC Design. 3.1 Front-End Design Phase. 3.2 Architectural Design Phase: The xpipes NoC Library. 3.3 Summary. 4 Designing Standard Topologies. 4.1 On-Chip Traffic Modeling. 4.2 Problem Formulation. 4.3 Mapping and Physical Planning Algorithm. 4.4 Physical Planning. 4.5 Experiments and Case Studies. 4.6 Summary. 5 Designing Custom Topologies. 5.1 Objectives. 5.2 Input Models. 5.3 Design Algorithms. 5.4 Experiments and Case Studies. 5.5 Summary. 6 Supporting Multiple Applications. 6.1 The Aethereal NoC Architecture. 6.2 Design Methodology. 6.3 Use-Case Pre-Processing. 6.4 Unified Mapping-NoC Configuration. 6.5 Simulation Results. 6.6 Summary. 7 Supporting Dynamic Application Patterns. 7.1 NoC Design Challenges for CMPs. 7.2 Basics of the Synthesis Approach. 7.3 Design Flow. 7.4 Problem Formulation. 7.5 Synthesis Algorithm. 7.6 Experimental Results. 7.7 Summary. Part II NoC Reliability Mechanisms 8 Timing-Error Tolerant NoC Design. 8.1 The Double Sampling Technique. 8.2 Using Links as a Storage Medium. 8.3 T-error Link Designs. 8.4 Aggressive Switch/NI Design. 8.5 Dynamic Configuration of the NoC. 8.6 Experimental Results. 8.7 Summary. 9 Analysis of NoC Error Recovery Schemes. 9.1 Switch Architecture Design. 9.2 Energy Estimation and Models. 9.3 Experiments and Simulation Results. 9.4 Summary. 10 Fault-Tolerant Route Generation. 10.1 Multi-Path Routing with In-Order Delivery. 10.2 Path Selection Algorithm. 10.3 Multi-path Traffic Splitting. 10.4 Fault-Tolerance Support with Multi-path Routing. 10.5 Simulation Results. 10.6 Summary. 11 NoC Support for Reliable On-Chip Memories. 11.1 Analysis of Multimedia Software. 11.2 Baseline SoC Architecture and Extensions. 11.3 Run-time Fault Tolerant Schemes. 11.4 Experimental Results. 11.5 Summary. 12 Conclusions and Future Directions. 12.1 Putting it All Together. Bibliography.

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You Can Find This Book In

Non-Fiction Computing & I.T.Computer Networking & Communications Science Physics Electricity Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computer Science Computer Architecture & Logic Design

Technology in General Engineering in General Energy Technology & Engineering Electrical Engineering Power Networks Mechanical Engineering & Materials Mechanical Engineering

Preface	p. v
Introduction	p. 1
Networks on Chips: Scalable Interconnects for SoCs	p. 1
NoC Design Challenges	p. 4
Book Overview	p. 5
NoC Design Methods	p. 5
NoC Reliability Mechanisms	p. 7
Related Work	p. 7
NoC Architectures and Design Methods	p. 8
Reliability Support for NoCs	p. 10
NoC Design Methods
Designing Crossbar Based Systems	p. 15
Problem Motivation and Application Traffic Analysis	p. 17
Problem Motivation	p. 17
Application Traffic Analysis	p. 19
Design Methodology	p. 19
Exact Approach to Crossbar Synthesis	p. 22
Problem Formulation	p. 22
Exact Crossbar Synthesis Algorithm	p. 24
Heuristic Approach to Crossbar Synthesis	p. 24
Experiments and Case Studies	p. 28
Experimental Platform and Power Models	p. 28
Application Benchmark Analysis	p. 29
Comparisons of Heuristic Engine with the Exact Engine	p. 32
Window Sizing	p. 34
Real-Time Streams & Effect of Binding	p. 36
Overlap Threshold Setting	p. 36
Summary	p. 37
Netchip Tool Flow for NoC Design	p. 39
Front-End Design Phase	p. 39
Architectural Design Phase: The x pipes NoC Library	p. 40
Summary	p. 42
Designing Standard Topologies	p. 43
On-Chip Traffic Modeling	p. 45
Problem Formulation	p. 47
Mapping and Physical Planning Algorithm	p. 50
Physical Planning	p. 51
Experiments and Case Studies	p. 53
Effect of Physical Planning	p. 53
Design for QoS Guarantees	p. 53
VOPD Design	p. 54
Buffer Sizing and Network Optimization	p. 54
Summary	p. 56
Designing Custom Topologies	p. 57
Objectives	p. 57
Background on NoC Topology Synthesis	p. 58
Background on Deadlock-Free NoC Design	p. 59
Input Models	p. 60
Area, Power Models	p. 60
Traffic Models	p. 62
Design Algorithms	p. 62
Experiments and Case Studies	p. 68
Experiments on MPSoC Benchmarks	p. 68
Layout-Level Comparisons	p. 70
Impact of Frequency Constraints	p. 72
Handling Dynamic Effects	p. 74
Summary	p. 74
Supporting Multiple Applications	p. 77
The &AE;thereal NoC Architecture	p. 78
Switch/NI Architecture	p. 79
Dynamic NoC Reconfiguration	p. 79
Design Methodology	p. 80
Use-Case Preprocessing	p. 82
Unified Mapping-NoC Configuration	p. 83
Simulation Results	p. 89
Experimental Benchmarks	p. 89
Effect of Mapping for SoC Benchmarks	p. 90
Frequency-Area Trade-offs	p. 90
Dynamic Configuration	p. 92
Parallel Use-Cases	p. 93
Summary	p. 93
Supporting Dynamic Application Patterns	p. 95
NoC Design Challenges for CMPs	p. 95
Basics of the Synthesis Approach	p. 97
Design Flow	p. 98
Problem Formulation	p. 99
Synthesis Algorithm	p. 101
NoC Link Sizing	p. 102
Timing Feasibility Check	p. 105
Algorithm Run-Time	p. 105
Experimental Results	p. 105
Experiments on a Mesh Topology	p. 106
Effect of Core Injection Rates	p. 107
Effect of Different NoC Sizes	p. 108
Effect of Link Length	p. 110
Application to Torus Topology	p. 110
Validating Design Flow Predictability	p. 111
Summary	p. 112
NoC Reliability Mechanisms
Timing-Error Tolerant NoC Design	p. 117
The Double Sampling Technique	p. 118
Using Links as a Storage Medium	p. 120
T-error Link Designs	p. 123
Scheme 1: Low overhead T-error Links	p. 123
Scheme 2: High-Performance T-error Links	p. 126
Aggressive Switch/NI Design	p. 128
Output Buffer Changes	p. 128
Input Buffer Changes	p. 129
Dynamic Configuration of the NoC	p. 130
Experimental Results	p. 131
Simulation Platform	p. 131
Experiments on a Multi-Media Benchmark	p. 131
Effect of Application-Level Power Management	p. 134
Experiments on Other Benchmarks	p. 134
Effect of NoC Configuration	p. 138
Choice of Link Design Schemes	p. 138
Synthesis Results	p. 139
Summary	p. 139
Analysis of NoC Error Recovery Schemes	p. 141
Switch Architecture Design	p. 142
End-to-End Error Detection	p. 142
Switch-to-Switch Error Detection	p. 143
Hybrid Single Error Correcting, Multiple Error Detecting Scheme	p. 143
Energy Estimation and Models	p. 144
Energy Estimation	p. 144
Error Models	p. 144
Experiments and Simulation Results	p. 144
Power Consumption of Schemes for Fixed Residual Error Rates	p. 144
Performance Comparison of Reliability Schemes	p. 146
Power Consumption Overhead of Reliability Schemes	p. 146
Effect of Buffering Requirements, Traffic Patterns and Packet Size	p. 149
Summary	p. 151
Fault-Tolerant Route Generation	p. 153
Multi-Path Routing with In-Order Delivery	p. 155
Path Selection Algorithm	p. 156
Multipath Traffic Splitting	p. 160
Fault-Tolerance Support with Multipath Routing	p. 161
Resilience Against Transient Errors	p. 161
Resilience Against Permanent Errors	p. 162
Simulation Results	p. 164
Area, Power and Timing Overhead	p. 164
Case Study: MPEG Decoder	p. 164
Comparisons with Single-Path Routing	p. 165
Effect of Fault-Tolerance Support	p. 166
Summary	p. 167
NoC Support for Reliable On-Chip Memories	p. 169
Analysis of Multimedia Software	p. 170
Baseline SoC Architecture and Extensions	p. 172
SoC Template Architecture	p. 172
Proposed Hardware Extensions	p. 173
Run-Time Fault Tolerant Schemes	p. 176
Permanent Error Recovery Support	p. 177
Intermittent Error Recovery Support	p. 178
Experimental Results	p. 178
Performance Studies	p. 179
Architectural Exploration of NoC Features	p. 182
Effects of Varying Percentages of Critical Data	p. 183
Synthesis Results	p. 184
Summary	p. 186
Conclusions and Future Directions	p. 187
Putting It All Together	p. 187
Bibliography	p. 191
Table of Contents provided by Ingram. All Rights Reserved.

Lecture Notes in Electrical Engineering

At a Glance

Hardcover

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