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Designing Reliable and Efficient Networks on Chips : Proceedings from the 7th International Workshop on Multi-Carrier Systems and Solutions, May 2009, Herrsching, Germany - Srinivasan Murali

Designing Reliable and Efficient Networks on Chips

Proceedings from the 7th International Workshop on Multi-Carrier Systems and Solutions, May 2009, Herrsching, Germany

By: Srinivasan Murali

eText | 26 May 2009

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Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
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Non-FictionComputing & I.T.Computer ScienceComputer Architecture & Logic DesignDatabasesData Capture & AnalysisComputer Networking & CommunicationsEngineering & TechnologyEnergy Technology & EngineeringElectrical EngineeringElectronics & Communications EngineeringElectronics Engineering
Circuits & ComponentsTechnology in GeneralEngineering in GeneralSystems Analysis & DesignMechanical Engineering & MaterialsMechanical Engineering

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