System-on-Chip Test Architectures

Nanometer Design for Testability

By: Nur Touba, Charles Stroud, Laung-Terng Wang

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Hardcover | 20 November 2007

At a Glance

Hardcover
896 Pages

Dimensions(cm)
24.13 x 19.05 x 3.81

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Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost.

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
Practical problems at the end of each chapter for students.

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Introduction
Digital Test Architectures
Fault-Tolerant Design
SOC/NOC Test Architectures
SIP Test Architectures
Delay Testing
Low-Power Testing
Coping with Physical Failures, Soft Errors, and Reliability Issues
Design for Manufacturability and Yield
Design for Debug and Diagnosis
Software-Based Self-Testing
FPGA Testing
MEMS Testing
High-Speed I/O Interface
Analog and Mixed-Signal Test Architectures
RF Testing
Testing Aspects of Nanotechnology Trends
Table of Contents provided by Publisher. All Rights Reserved.

System-on-Chip Test Architectures

Nanometer Design for Testability

At a Glance

Hardcover

Shipping

How to return your order

Defective items

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