Planar Double-Gate Transistor

From technology to circuit

By: Amara Amara (Editor), Olivier Rozeau (Editor)

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Hardcover | 30 January 2009

At a Glance

Hardcover
224 Pages

Dimensions(cm)
24.13 x 16.51 x 1.27

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Until the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called "scaling", has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore's Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving signi?cantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, signi?cant issues appeared such as the increase of the circuit heating, device complexity, variability and dif?culties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore's law and each dif?culty has found a solution.

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Electronic Devices & Materials Transistors Other Technologies & Applied Sciences Applied Optics Science Physics Materials & States of Matter Circuits & Components

Chemistry Analytical Chemistry Spectrum Analysis Mechanical Engineering & Materials Materials Science

Introduction
Multiple Gate Technologies
Introduction
Advantages of multiple gate technologies
Planar double gate technologies
Non planar multiple gate technologies
Conclusions and perspectives. References
Compact Modeling of Independent Double-Gate Mosfet: a Physical Approach
Introduction
Drift-diffusion Drain current modeling
Ballistic current in the subthreshold regime
Conclusion.References
Compact Modeling of Double Gate MOSFET for IC Design
Introduction
Modeling of Independent Gate MOSFET With Independent Driven Gates
Long channel IDG MOSFET Threshold voltage based model
Short channel effects
Conclusion.References
Low Frequency Noise in Double-Gate SOI CMOS Devices
Introduction
Low Frequency Noise Analysis
Results and Discussions
Conclusion.References
Analog Circuit Design
Double Gate MOSFET In Analog Design
Current Mirrors
Differential Pairs
Low Voltage OTAS
High Speed Comparators
Conclusion.References
Logic Circuit Design With DGMOS Devices
DGMOS characteristics and impact on digital design
Standard cells using DGMOS
Ultra Low Power full-adder using Double gate SOI devices
DGMOS DEVICE based reconfigurable cells. References
SRAM Circuit Design
Introduction
SRAM memories
Double gate 6T SRAM memories
Double gate 4T & 5T SRAM memories
References
Conclusion
Appendix
Index
Table of Contents provided by Publisher. All Rights Reserved.

Planar Double-Gate Transistor

From technology to circuit

At a Glance

Hardcover

Shipping

How to return your order

Defective items

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