Network Processors : A Volume in the Systems on Silicon Series - Ran Giladi

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Network Processors

A Volume in the Systems on Silicon Series

By: Ran Giladi

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Hardcover | 16 July 2008 | Edition Number 1

At a Glance

Hardcover
736 Pages

Dimensions(cm)
23.5 x 20.32 x 4.45

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Network processors are the basic building blocks of today's high-speed, high-demand, quality-oriented communication networks. Designing and implementing network processors requires a new programming paradigm and an in-depth understanding of network processing requirements. This book leads the reader through the requirements and the underlying theory of networks, network processing, and network processors. It covers implementation of network processors and intergrates EZchip Microcode Development Environment so that you can gain hands-on experience in writing high-speed networking applications. By the end of the book, the reader will be able to write and test applications on a simulated network processor.

Comprehensive, theoretical, and pracitical coverage of networks and high-speed networking applications
Descirbes contemporary core, metro, and access networks and their processing algorithms
Covers network processor architectures and programming models, enabling readers to assess the optimal network processor typer and configuration for their application
Free download from http://www.cse.bgu.ac.il/npbook includes microcode development tools that provide hands-on experience with programming a network processor

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Preface	p. xi
Introduction and Motivation	p. 1
Network Processors Ecosystem	p. 1
Communication Systems and Applications	p. 2
Network Elements	p. 6
Network Processors	p. 8
Structure of This Book	p. 10
Summary	p. 12
Networks
Networking Fundamentals	p. 15
Introduction	p. 16
Networks Primer	p. 17
Data Networking Models	p. 21
Basic Network Technologies	p. 25
Telecom Networks	p. 26
Data Networks	p. 38
Summary	p. 69
Appendix A	p. 70
Appendix B	p. 72
Converged Networks	p. 77
Introduction	p. 77
From Telecom Networks to Data Networks	p. 78
From Datacom to Telecom	p. 87
Summary	p. 134
Appendix A	p. 135
Access and Home Networks	p. 149
Access Networks	p. 149
Home and Building Networks	p. 178
Summary	p. 180
Processing
Packet Processing	p. 183
Introduction and Definitions	p. 183
Ingress and Egress	p. 186
Framing	p. 188
Parsing and Classification	p. 195
Search, Lookup, and Forwarding	p. 205
Modification	p. 236
Compression and Encryption	p. 237
Queueing and Traffic Management	p. 238
Summary	p. 239
Packet Flow Handling	p. 241
Definitions	p. 242
Quality of Service	p. 243
Class of Service	p. 244
QoS Mechanisms	p. 249
Summary	p. 286
Architecture	p. 287
Introduction	p. 287
Background and Definitions	p. 289
Equipment Design Alternatives:ASICs versus NP	p. 308
Network Processors Basic Architectures	p. 309
Instruction Set (Scalability; Processing Speed)	p. 314
NP Components	p. 314
Summary	p. 335
Software	p. 337
Introduction	p. 338
Conventional Systems	p. 342
Programming Models Classification	p. 348
Parallel Programming	p. 349
Pipelining	p. 355
Network Processor Programming	p. 359
Summary	p. 363
Appendix A	p. 364
Appendix B	p. 371
Appendix C	p. 377
NP Peripherals	p. 379
Switch Fabrics	p. 379
CoProcessors	p. 403
Summary	p. 407
A Network Processor: EZchip
EZchip Architecture, Capabilities, and Applications	p. 411
General description	p. 411
System Architecture	p. 413
Lookup Structures	p. 419
Counters, Statistics and Rate Control	p. 421
Traffic Management	p. 424
Stateful Classification	p. 425
Multicast Frames	p. 425
Data Flow	p. 426
Summary	p. 438
EZchip Programming	p. 439
Instruction Pipeline	p. 440
Writing NP Microcode	p. 443
Preprocessor Overview	p. 447
Developing and Running NP Applications	p. 447
TOP Common Commands	p. 449
Summary	p. 457
Appendix A	p. 458
Parsing	p. 461
Internal Engine Diagram	p. 461
TOPparse Registers	p. 465
TOPparse Structures	p. 469
TOPparse Instruction Set	p. 469
Example	p. 474
Summary	p. 478
Appendix A	p. 479
Appendix B	p. 486
Appendix C	p. 487
Searching	p. 501
Introduction	p. 501
Internal Engine Diagram	p. 502
TOPsearch I Structures	p. 505
Interface to TOPparse (Input to TOPsearch)	p. 506
Interface to TOPresolve (Output of TOPsearch)	p. 509
Hash Table Learning	p. 511
Example	p. 513
Summary	p. 516
Resolving	p. 517
Internal Engine Diagram	p. 517
TOPresolve Registers	p. 521
TOPresolve Structures	p. 526
TOPresolve Instruction Set	p. 527
Example	p. 531
Summary	p. 536
Appendix A	p. 537
Appendix B	p. 544
Appendix C	p. 546
Modifying	p. 561
Introduction	p. 561
Internal Engine Diagram	p. 563
TOPmodify Registers	p. 566
TOPmodify Structures	p. 570
TOPmodify Instruction Set	p. 571
Example	p. 574
Summary	p. 583
Appendix A	p. 584
Appendix B	p. 591
Appendix C	p. 592
Running the Virtual Local Area Network Example	p. 603
Installation	p. 603
Getting Started	p. 604
Microcode Development Workflow	p. 607
Summary	p. 615
Writing Your First High-Speed Network Application	p. 617
Introduction	p. 617
Data Flow and TOP Microcode	p. 618
Data Structures	p. 648
Summary	p. 654
List of Acronyms	p. 655
References	p. 673
Index	p. 695
Table of Contents provided by Ingram. All Rights Reserved.

Network Processors

A Volume in the Systems on Silicon Series

At a Glance

Hardcover

Shipping

How to return your order

Defective items

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