Intelligent Memory Systems : Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers - Frederic T. Chong

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Intelligent Memory Systems

Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers

By: Frederic T. Chong (Editor), Christoforos Kozyrakis (Editor), Mark Oskin (Editor)

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Paperback | 29 August 2001

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208 Pages

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24.13 x 15.88 x 1.27

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We are pleased to present this collection of papers from the Second Workshop on Intelligent Memory Systems. Increasing die densities and inter chip communication costs continue to fuel interest in intelligent memory systems. Since the First Workshop on Mixing Logic and DRAM in 1997, technologies and systems for computation in memory have developed quickly. The focus of this workshop was to bring together researchers from academia and industry to discuss recent progress and future goals. The program committee selected 8 papers and 6 poster session abstracts from 29 submissions for inclusion in the workshop. Four to five members of the program committee reviewed each submission and their reviews were used to numerically rank them and guide the selection process. We believe that the resulting program is of the highest quality and interest possible. The selected papers cover a wide range of research topics such as circuit technology, processor and memory system architecture, compilers, operating systems, and applications. They also present a mix of mature projects, work in progress, and new research ideas. The workshop also included two invited talks. Dr. Subramanian Iyer (IBM Microelectronics) provided an overview of embedded memory technology and its potential. Dr. Mark Snir (IBM Research) presented the Blue Gene, an aggressive supercomputer system based on intelligent memory technology.

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You Can Find This Book In

Non-Fiction Medicine Medicine in General Computing & I.T.Computer Networking & Communications Computer Science Artificial Intelligence Machine Learning Computer Hardware Maintenance & Repairs Systems Analysis & Design Operating Systems

Computer Architecture & Logic Design Computer Programming & Software Development Software Engineering

Memory Technology
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro	p. 1
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing	p. 15
Processor and Memory Architecture
Content-Based Prefetching: Initial Results	p. 33
Memory System Support for Dynamic Cache Line Assembly	p. 56
Adaptively Mapping Code in an Intelligent Memory Architecture	p. 71
Applications and Operating Systems
The Characterization of Date Intensive Memory Workloads on Distributed PIM Systems	p. 85
Memory Management in a PIM-Based Architecture	p. 104
Compiler Technology
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler	p. 122
FlexCache: A Framework for Flexible Compiler Generated Data Caching	p. 135
Poster Session
Aggressive Memory-Aware Compilation	p. 147
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips	p. 152
SAGE: A New Analysis and Optimization System for FlexRAM Architecture	p. 160
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems	p. 169
The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems	p. 179
Compiler-Directed Cache Line Size Adaptivity	p. 183
Workshop Notes	p. 188
Author Index	p. 193
Table of Contents provided by Publisher. All Rights Reserved.

Intelligent Memory Systems

Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers

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