Advanced Asic Chip Synthesis : Using Synopsis Design Compiler and Primetime

By: Himanshu Bhatnagar

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Hardcover
316 Pages

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23.0 x 17.78 x 2.54

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This book describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-arounds described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal s

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Foreword
Preface
Acknowledgements
About The Author
ASIC Design Methodology	p. 1
Tutorial	p. 15
Basic Concepts	p. 43
Synopsys Technology Library	p. 63
Partitioning and Coding Styles	p. 79
Constraining Designs	p. 99
Optimizing Designs	p. 121
Design for Test	p. 147
Links to Layout and Post-Layout Opt	p. 159
SDF Generation	p. 195
Primetime Basics	p. 209
Static Timing Analysis	p. 231
Appendix	p. 275
Index	p. 277
Table of Contents provided by Blackwell. All Rights Reserved.

Advanced Asic Chip Synthesis : Using Synopsis Design Compiler and Primetime

At a Glance

Hardcover

Shipping

How to return your order

Defective items

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