A Pipelined Multi-core MIPS Machine

1 Introduction.-1.1 Motivation.- 1.2 Overview.- 2 Number Formats and Boolean Algebra.- 2.1 Basics.- 2.1.1 Numbers, Sets, and Logical Connectives.- 2.1.2 Sequences and Bit-Strings.- 2.2 Modulo Computation.- 2.3 Geometric Sums.- 2.4 Binary Numbers.- 2.5 Two's Complement Numbers.- 2.6 Boolean Algebra.- 2.6.1 Identities.- 2.6.2 Solving Equations.- 2.6.3 Disjunctive Normal Form.- 3 Hardware.- 3.1 Digital Gates and Circuits.- 3.2 Some Basic Circuits.- 3.3 Clocked Circuits.- 3.3.1 Digital Clocked Circuits.- 3.3.2 The Detailed Hardware Model.- 3.3.3 Timing Analysis.- 3.4 Registers.- 3.5 Drivers and Main Memory.- 3.5.1 Open Collector Drivers and Active Low Signal.- 3.5.2 Tristate Drivers and Bus Contention.- 3.5.3 The Incomplete Digital Model for Drivers.- 3.5.4 Self Destructing Hardware.- 3.5.5 Clean Operation of Tristate Buses.- 3.5.6 Specification of Main Memory.- 3.5.7 Operation of Main Memory via a Tristate Bus.- 3.6 Finite State Transducers.- 3.6.1 Realization of Moore Automata.- 3.6.2 Precomputing Outputs of Moore Automata.- 3.6.3 Realization of Mealy Automata.- 3.6.4 Precomputing Outputs of Mealy Automata.- 4 Nine Shades of RAM.- 4.1 Basic Random Access Memory.- 4.2 Single-Port RAM Designs.- 4.2.1 Read Only Memory (ROM).- 4.2.2 Multi-bank RAM.- 4.2.3 Cache State RAM.- 4.2.4 SPR RAM.- 4.3 Multi-port RAM Designs.- 4.3.1 3-port RAM for General Purpose Registers.- 4.3.2 General 2-port RAM.- 4.3.3 2-port Multi-bank RAM-ROM.- 4.3.4 2-port Cache State RAM.- 5 Arithmetic Circuits.- 5.1 Adder and Incrementer.- 5.2 Arithmetic Unit.- 5.3 Arithmetic Logic Unit (ALU).- 5.4 Shift Unit.- 5.5 Branch Condition Evaluation Unit.- 6 A Basic Sequential MIPS Machine.- 6.1 Tables.- 6.1.1 I-type.- 6.1.2 R-type.- 6.1.3 J-type.- 6.2 MIPS ISA.- 6.2.1 Configuration and Instruction Fields.- 6.2.2 Instruction Decoding.- 6.2.3 ALU-Operations.- 6.2.4 Shift Unit Operations.- 6.2.5 Branch and Jump.- 6.2.6 Sequences of Consecutive Memory Bytes.- 6.2.7 Loads and Stores.- 6.2.8 ISA Summary.- 6.3 A Sequential Processor Design.- 6.3.1 Software Conditions.- 6.3.2 Hardware Configurations and Computations.- 6.3.3 Memory Embedding.- 6.3.4 Defining Correctness for the Processor Design.- 6.3.5 Stages of Instruction Execution.- 6.3.6 Initialization.- 6.3.7 Instruction Fetch.- 6.3.8 Instruction Decoder.- 6.3.9 Reading from General Purpose Registers.- 6.3.10 Next PC Environment.- 6.3.11 ALU Environment.- 6.3.12 Shift Unit Environment.- 6.3.13 Jump and Link.- 6.3.14 Collecting Results.- 6.3.15 Effective Address.- 6.3.16 Shift for Store Environment.- 6.3.17 Memory Stage.- 6.3.18 Shifter for Load.- 6.3.19 Writing to the General Purpose Register File.- 7 Pipelining.- 7.1 MIPS ISA and Basic Implementation Revisited.- 7.1.1 Delayed PC.- 7.1.2 Implementing the Delayed PC.- 7.1.3 Pipeline Stages and Visible Registers.- 7.2 Basic Pipelined Processor Design.- 7.2.1 Transforming the Sequential Design.- 7.2.2 Scheduling Functions.- 7.2.3 Use of Invisible Registers.- 7.2.4 Software Condition SC-1.- 7.2.5 Correctness Statement.- 7.2.6 Correctness Proof of the Basic Pipelined Design.- 7.3 Forwarding.- 7.3.1 Hits.- 7.3.2 Forwarding Circuits.- 7.3.3 Software Condition SC-2.- 7.3.4 Scheduling Functions Revisited.- 7.3.5 Correctness Proof.- 7.4 Stalling 7.4.1 Stall Engine.- 7.4.2 Hazard Signals.- 7.4.3 Correctness Statement.- 7.4.4 Scheduling Functions.- 7.4.5 Correctness Proof.- 7.4.6 Liveness.- 8 Caches and Shared Memory.- 8.1 Concrete and Abstract Caches.- 8.1.1 Abstract Caches and Cache Coherence.- 8.1.2 Direct Mapped Caches.- 8.1.3 k-way Associative Caches.- 8.1.4 Fully Associative Caches.- 8.2 Notation.- 8.2.1 Parameters.- 8.2.2 Memory and Memory Systems.- 8.2.3 Accesses and Access Sequences.- 8.2.4 Sequential Memory Semantics.- 8.2.5 Sequentially Consistent Memory Systems.- 8.2.6 Memory System Hardware Configurations.- 8.3 Atomic MOESI Protocol.- 8.3.1 Invariants.- 8.3.2 Defining the Protocol by Tables.- 8.3.3 Translating the Tables into Switching Functions.- 8.3.4 Algebraic Specification.- 8.3.5 Properties of the Atomic Protocol.- 8.4 Gate Level Design of a Shared Memory System.- 8.4.1 Specification of Interfaces.- 8.4.2 Data Paths of Caches.- 8.4.3 Cache Protocol Automata.- 8.4.4 Automata Transitions and Control Signals.- 8.4.5 Bus Arbiter.- 8.4.6 Initialization.- 8.5 Correctness Proof.- 8.5.1 Arbitration.- 8.5.2 Silent Slaves and Silent Masters.- 8.5.3 Automata Synchronization.- 8.5.4 Control of Tristate Drivers.- 8.5.5 Protocol Data Transmission.- 8.5.6 Data Transmission.- 8.5.7 Accesses of the Hardware Computation.- 8.5.8 Relation with the Atomic Protocol.- 8.5.9 Ordering Hardware Accesses Sequentially.- 8.5.10 Sequential Consistency.- 8.5.11 Liveness.- 9 A Multi-core Processor.- 9.1 Compare-and-Swap Instruction.- 9.1.1 Introducing CAS to the ISA .- 9.1.2 Introducing CAS to the Sequential Processor.- 9.2 Multi-core ISA and Reference Implementation.- 9.2.1 Multi-core ISA Specification.- 9.2.2 Sequential Reference Implementation.- 9.2.3 Simulation Relation.- 9.2.4 Local Configurations and Computations.- 9.2.5 Accesses of the Reference Computation.- 9.3 Shared Memory in the Multi-core System.- 9.3.1 Notation.- 9.3.2 Invisible Registers and Hazard Signals.- 9.3.3 Connecting Interfaces.- 9.3.4 Stability of Inputs of Accesses.- 9.3.5 Relating Update Enable Signals and Ends of Accesses.- 9.3.6 Scheduling Functions.- 9.3.7 Stepping Function.- 9.3.8 Correctness Proof.- 9.3.9 Liveness.- References.- Index.