3D Stacked Chips

From Emerging Processes to Heterogeneous Systems

By: Ibrahim (Abe) M. Elfadel (Editor), Gerhard Fettweis (Editor)

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Hardcover | 23 May 2016

At a Glance

Hardcover
364 Pages

Dimensions(cm)
24.13 x 16.51 x 2.54

Hardcover

$84.99

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This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size. The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.

Industry Reviews

"The book is valuable as a learning tool for 3D stacked chips through TSVs ... . a valuable addition to a scientific library, as well as served as good introduction for device reliability engineers or specialists and industrials involved in the field of 3D stacking in wafer fabrication and integrated circuit design. ... highly recommended for people who desire a better understanding of the theory and practice of 3D TSVs and technical considerations in 3D chips floorplanning, modeling and characterization." (Chong Leong Gan and Uda Hashim, Microelectronics Reliability, Vol. 63, August, 2016)

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