Verification by Error Modeling

Using Testing Techniques in Hardware Verification

By: Katarzyna Radecka, Zeljko Zilic

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Hardcover | 30 November 2003

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236 Pages

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24.13 x 15.88 x 1.27

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1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be "imminently doable" by Intel fellow J. Crawford at Microprocessor Forum in October 2002 40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.

Industry Reviews

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"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. ... The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)

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You Can Find This Book In

Non-Fiction Computing & I.T.Computer Programming & Software Development Software Engineering Software Testing & Verification Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computer Science Computer Architecture & Logic Design Energy Technology & Engineering

Electrical Engineering Automatic Control Engineering Robotics Graphical & Digital Media Applications Artificial Intelligence

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Published: 7th December 2010

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List of Figures	p. xi
Acknowledgments	p. xv
Introduction	p. 1
Design Flow	p. 1
Verification--Approaches and Problems	p. 4
Verification Approaches	p. 5
Verification by Simulations	p. 5
Test Vector Generation	p. 5
Design Error Models	p. 7
Other Simulation Methods	p. 9
Coverage Verification	p. 9
Other Metrics	p. 10
Formal Verification	p. 11
Model-based Formal Verification Methods	p. 12
Proof-theoretical Formal Verification Methods	p. 14
Spectral Methods in Verification	p. 14
Book Objectives	p. 15
Boolean Function Representations	p. 19
Background--Function Representations	p. 19
Truth Tables	p. 20
Boolean Equations--Sum of Products	p. 21
Satisfiability of Boolean Functions	p. 23
Algorithms for Solving Satisfiability	p. 24
Shannon Expansion	p. 28
Polynomial Representation	p. 28
Decision Diagrams	p. 30
Reduced Ordered Binary Decision Diagrams	p. 31
Word-Level Decision Diagrams	p. 33
Binary Moment Diagrams	p. 33
Limitations of WLDDs	p. 35
Spectral Representations	p. 38
Walsh-Hadamard Transform	p. 39
Walsh Transform Variations	p. 40
Walsh-Hadamard Transform as Fourier Transform	p. 41
Arithmetic Transform	p. 44
Calculation of Arithmetic Transform	p. 47
Fast Arithmetic Transform	p. 47
Boolean Lattice and AT Calculation	p. 48
AT and Word-Level Decision Diagrams	p. 49
Don't Cares and Their Calculation	p. 51
Incompletely Specified Boolean Functions	p. 51
Don't Cares in Logic Synthesis	p. 51
Don't Cares in Testing for Manufacturing Faults	p. 52
Don't Cares in Circuit Verification	p. 54
Using Don't Cares for Redundancy Identification	p. 55
Basic Definitions	p. 56
Calculation of All Don't Care Conditions	p. 57
Computation of Controllability Don't Cares	p. 57
Algorithms for Determining CDCs	p. 59
Algorithms for Computing ODCs	p. 65
Approximations to Observability Don't Cares--CODCs	p. 67
Testing	p. 71
Introduction	p. 71
Fault List Reduction	p. 73
Overview of Simulators	p. 73
True-Value Simulator Types	p. 74
Logic Simulators	p. 75
Fault Simulators	p. 79
Random Simulations	p. 81
Linear Feedback Shift Registers	p. 82
Other Pseudo-Random Test Pattern Generators	p. 88
Final remarks	p. 93
Deterministic Vector Generation--ATPG	p. 94
Deterministic Phase	p. 94
Search for Vectors	p. 98
Fault Diagnosis	p. 100
Conclusions	p. 101
Design Error Models	p. 103
Introduction	p. 103
Design Errors	p. 105
Explicit Design Error Models	p. 107
Detecting Explicit Errors	p. 110
Application of Stuck-at-value Vector Set	p. 110
Detection of Gate Replacements	p. 110
Universal Test Set Approach	p. 111
Implicit Error Model Precursors	p. 112
Rationale for Implicit Models	p. 113
Related Work--Error Models	p. 114
Port Fault Models	p. 114
Additive Implicit Error Model	p. 115
Arithmetic Transform of Basic Design Errors	p. 117
Design Error Detection and Correction	p. 123
Path Trace Procedure	p. 125
Back-propagation	p. 126
Boolean Difference Approximation by Simulations	p. 127
Conclusions	p. 128
Design Verification by AT	p. 129
Introduction	p. 129
Detecting Small AT Errors	p. 132
Universal Test Set	p. 132
AT-based Universal Diagnosis Set	p. 133
Bounding Error by Walsh Transform	p. 135
Spectrum Comparison	p. 137
Spectrum Distribution and Partial Spectra Comparison	p. 138
Absolute Value Comparison	p. 140
Experimental Results	p. 142
Improvements--Neighborhood Subspace Points	p. 145
Conclusions	p. 146
Identifying redundant gate and wire replacements	p. 147
Introduction	p. 147
Gate Replacement Faults	p. 149
Redundant Replacement Faults	p. 150
Overview of the Proposed Approach	p. 151
Redundancy Detection by Don't Cares	p. 151
Using Local Don't Cares	p. 152
Using Testing--Single Minterm Approximation	p. 154
Redundant Single Cube Replacements	p. 159
Use of SAT in Redundancy Identification	p. 160
Passing Proximity Information to SAT	p. 161
Exact Redundant Fault Identification	p. 163
Preprocessing	p. 164
Identifying Redundant Wire Replacements	p. 164
Wire Replacement Faults and Rewiring	p. 166
Detection by Don't Cares	p. 167
Don't Care Approximations	p. 169
SAT for Redundant Wire Identification	p. 170
Approximate Redundancy Identification	p. 171
Exact Wire Redundancy IDentification	p. 172
I/O Port Replacement Detection	p. 175
Detection of I/O Port Wire Switching Errors	p. 175
Experimental Results	p. 177
Gate Replacement Experiments	p. 177
Minimum Distance Replacements	p. 177
Wire Replacement Experiments	p. 182
True Fan-in Acyclic Replacements	p. 184
SAT vs. ATPG	p. 185
Conclusions	p. 185
Conclusions and future work	p. 187
Conclusions	p. 187
Future Work	p. 189
Appendices	p. 191
References	p. 197
Index	p. 211
Table of Contents provided by Ingram. All Rights Reserved.

Verification by Error Modeling

Using Testing Techniques in Hardware Verification

At a Glance

Hardcover

Industry Reviews

Shipping

How to return your order

Defective items

You Can Find This Book In

Other Editions and Formats

Paperback

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