| Preface | p. xv |
| From the Old to the New | p. xvii |
| Acknowledgments | p. xxi |
| Verilog - A Tutorial Introduction | p. 1 |
| Getting Started | p. 2 |
| A Structural Description | p. 2 |
| Simulating the binaryToESeg Driver | p. 4 |
| Creating Ports For the Module | p. 7 |
| Creating a Testbench For a Module | p. 8 |
| Behavioral Modeling of Combinational Circuits | p. 11 |
| Procedural Models | p. 12 |
| Rules for Synthesizing Combinational Circuits | p. 13 |
| Procedural Modeling of Clocked Sequential Circuits | p. 14 |
| Modeling Finite State Machines | p. 15 |
| Rules for Synthesizing Sequential Systems | p. 18 |
| Non-Blocking Assignment ("<=") | p. 19 |
| Module Hierarchy | p. 21 |
| The Counter | p. 21 |
| A Clock for the System | p. 21 |
| Tying the Whole Circuit Together | p. 22 |
| Tying Behavioral and Structural Models Together | p. 25 |
| Summary | p. 27 |
| Exercises | p. 28 |
| Logic Synthesis | p. 35 |
| Overview of Synthesis | p. 35 |
| Register-Transfer Level Systems | p. 35 |
| Disclaimer | p. 36 |
| Combinational Logic Using Gates and Continuous Assign | p. 37 |
| Procedural Statements to Specify Combinational Logic | p. 40 |
| The Basics | p. 40 |
| Complications--Inferred Latches | p. 42 |
| Using Case Statements | p. 43 |
| Specifying Don't Care Situations | p. 44 |
| Procedural Loop Constructs | p. 46 |
| Inferring Sequential Elements | p. 48 |
| Latch Inferences | p. 48 |
| Flip Flop Inferences | p. 50 |
| Summary | p. 52 |
| Inferring Tri-State Devices | p. 52 |
| Describing Finite State Machines | p. 53 |
| An Example of a Finite State Machine | p. 53 |
| An Alternate Approach to FSM Specification | p. 56 |
| Finite State Machine and Datapath | p. 58 |
| A Simple Computation | p. 58 |
| A Datapath For Our System | p. 58 |
| Details of the Functional Datapath Modules | p. 60 |
| Wiring the Datapath Together | p. 61 |
| Specifying the FSM | p. 63 |
| Summary on Logic Synthesis | p. 66 |
| Exercises | p. 68 |
| Behavioral Modeling | p. 73 |
| Process Model | p. 73 |
| If-Then-Else | p. 75 |
| Where Does The ELSE Belong? | p. 80 |
| The Conditional Operator | p. 81 |
| Loops | p. 82 |
| Four Basic Loop Statements | p. 82 |
| Exiting Loops on Exceptional Conditions | p. 85 |
| Multi-way Branching | p. 86 |
| If-Else-If | p. 86 |
| Case | p. 86 |
| Comparison of Case and If-Else-If | p. 89 |
| Casez and Casex | p. 90 |
| Functions and Tasks | p. 91 |
| Tasks | p. 93 |
| Functions | p. 97 |
| A Structural View | p. 100 |
| Rules of Scope and Hierarchical Names | p. 102 |
| Rules of Scope | p. 102 |
| Hierarchical Names | p. 105 |
| Summary | p. 106 |
| Exercises | p. 106 |
| Concurrent Processes | p. 109 |
| Concurrent Processes | p. 109 |
| Events | p. 111 |
| Event Control Statement | p. 112 |
| Named Events | p. 113 |
| The Wait Statement | p. 116 |
| A Complete Producer-Consumer Handshake | p. 117 |
| Comparison of the Wait and While Statements | p. 120 |
| Comparison of Wait and Event Control Statements | p. 121 |
| A Concurrent Process Example | p. 122 |
| A Simple Pipelined Processor | p. 128 |
| The Basic Processor | p. 128 |
| Synchronization Between Pipestages | p. 130 |
| Disabling Named Blocks | p. 132 |
| Intra-Assignment Control and Timing Events | p. 134 |
| Procedural Continuous Assignment | p. 136 |
| Sequential and Parallel Blocks | p. 138 |
| Exercises | p. 140 |
| Module Hierarchy | p. 143 |
| Module Instantiation and Port Specifications | p. 143 |
| Parameters | p. 146 |
| Arrays of Instances | p. 150 |
| Generate Blocks | p. 151 |
| Exercises | p. 154 |
| Logic Level Modeling | p. 157 |
| Introduction | p. 157 |
| Logic Gates and Nets | p. 158 |
| Modeling Using Primitive Logic Gates | p. 159 |
| Four-Level Logic Values | p. 162 |
| Nets | p. 163 |
| A Logic Level Example | p. 166 |
| Continuous Assignment | p. 171 |
| Behavioral Modeling of Combination Circuits | p. 172 |
| Net and Continuous Assign Declarations | p. 174 |
| A Mixed Behavioral/Structural Example | p. 176 |
| Logic Delay Modeling | p. 180 |
| A Gate Level Modeling Example | p. 181 |
| Gate and Net Delays | p. 182 |
| Specifying Time Units | p. 185 |
| Minimum, Typical, and Maximum Delays | p. 186 |
| Delay Paths Across a Module | p. 187 |
| Summary of Assignment Statements | p. 189 |
| Summary | p. 190 |
| Exercises | p. 191 |
| Cycle-Accurate Specification | p. 195 |
| Cycle-Accurate Behavioral Descriptions | p. 195 |
| Specification Approach | p. 195 |
| A Few Notes | p. 197 |
| Cycle-Accurate Specification | p. 198 |
| Inputs and Outputs of an Always Block | p. 198 |
| Input/Output Relationships of an Always Block | p. 199 |
| Specifying the Reset Function | p. 202 |
| Mealy/Moore Machine Specifications | p. 203 |
| A Complex Control Specification | p. 204 |
| Data and Control Path Trade-offs | p. 204 |
| Introduction to Behavioral Synthesis | p. 209 |
| Summary | p. 210 |
| Advanced Timing | p. 211 |
| Verilog Timing Models | p. 211 |
| Basic Model of a Simulator | p. 214 |
| Gate Level Simulation | p. 215 |
| Towards a More General Model | p. 215 |
| Scheduling Behavioral Models | p. 218 |
| Non-Deterministic Behavior of the Simulation Algorithm | p. 220 |
| Near a Black Hole | p. 221 |
| It's a Concurrent Language | p. 223 |
| Non-Blocking Procedural Assignments | p. 226 |
| Contrasting Blocking and Non-Blocking Assignments | p. 226 |
| Prevalent Usage of the Non-Blocking Assignment | p. 227 |
| Extending the Event-Driven Scheduling Algorithm | p. 228 |
| Illustrating Non-Blocking Assignments | p. 231 |
| Summary | p. 233 |
| Exercises | p. 234 |
| User-Defined Primitives | p. 239 |
| Combinational Primitives | p. 240 |
| Basic Features of User-Defined Primitives | p. 240 |
| Describing Combinational Logic Circuits | p. 242 |
| Sequential Primitives | p. 243 |
| Level-Sensitive Primitives | p. 244 |
| Edge-Sensitive Primitives | p. 244 |
| Shorthand Notation | p. 246 |
| Mixed Level- and Edge-Sensitive Primitives | p. 246 |
| Summary | p. 249 |
| Exercises | p. 249 |
| Switch Level Modeling | p. 251 |
| A Dynamic MOS Shift Register Example | p. 251 |
| Switch Level Modeling | p. 256 |
| Strength Modeling | p. 256 |
| Strength Definitions | p. 259 |
| An Example Using Strengths | p. 260 |
| Resistive MOS Gates | p. 262 |
| Ambiguous Strengths | p. 263 |
| Illustrations of Ambiguous Strengths | p. 264 |
| The Underlying Calculations | p. 265 |
| The miniSim Example | p. 270 |
| Overview | p. 270 |
| The miniSim Source | p. 271 |
| Simulation Results | p. 280 |
| Summary | p. 281 |
| Exercises | p. 281 |
| Projects | p. 283 |
| Modeling Power Dissipation | p. 283 |
| Modeling Power Dissipation | p. 284 |
| What to do | p. 284 |
| Steps | p. 285 |
| A Floppy Disk Controller | p. 286 |
| Introduction | p. 286 |
| Disk Format | p. 287 |
| Function Descriptions | p. 288 |
| Reality Sets In... | p. 291 |
| Everything You Always Wanted to Know about CRC's | p. 291 |
| Supporting Verilog Modules | p. 292 |
| Tutorial Questions and Discussion | p. 293 |
| Structural Descriptions | p. 293 |
| Testbench Modules | p. 303 |
| Combinational Circuits Using always | p. 303 |
| Sequential Circuits | p. 305 |
| Hierarchical Descriptions | p. 308 |
| Lexical Conventions | p. 309 |
| White Space and Comments | p. 309 |
| Operators | p. 310 |
| Numbers | p. 310 |
| Strings | p. 311 |
| Identifiers, System Names, and Keywords | p. 312 |
| Verilog Operators | p. 315 |
| Table of Operators | p. 315 |
| Operator Precedence | p. 320 |
| Operator Truth Tables | p. 321 |
| Expression Bit Lengths | p. 322 |
| Verilog Gate Types | p. 323 |
| Logic Gates | p. 323 |
| BUF and NOT Gates | p. 325 |
| BUFIF and NOTIF Gates | p. 326 |
| MOS Gates | p. 327 |
| Bidirectional Gates | p. 328 |
| CMOS Gates | p. 328 |
| Pullup and Pulldown Gates | p. 328 |
| Registers, Memories, Integers, and Time | p. 329 |
| Registers | p. 329 |
| Memories | p. 330 |
| Integers and Times | p. 331 |
| System Tasks and Functions | p. 333 |
| Display and Write Tasks | p. 333 |
| Continuous Monitoring | p. 334 |
| Strobed Monitoring | p. 335 |
| File Output | p. 335 |
| Simulation Time | p. 336 |
| Stop and Finish | p. 336 |
| Random | p. 336 |
| Reading Data From Disk Files | p. 337 |
| Formal Syntax Definition | p. 339 |
| Tutorial Guide to Formal Syntax Specification | p. 339 |
| Source text | p. 343 |
| Declarations | p. 346 |
| Primitive instances | p. 351 |
| Module and generated instantiation | p. 353 |
| UDP declaration and instantiation | p. 355 |
| Behavioral statements | p. 355 |
| Specify section | p. 359 |
| Expressions | p. 365 |
| General | p. 370 |
| Index | p. 373 |
| Table of Contents provided by Syndetics. All Rights Reserved. |
