Microprocessor Architecture : From Simple Pipelines to Chip Multiprocessors - Jean-Loup Baer

Instant online reading.
Don't wait for delivery!
Go digital and save!

Microprocessor Architecture

From Simple Pipelines to Chip Multiprocessors

By: Jean-Loup Baer

Write A Review

Hardcover | 7 December 2009

At a Glance

Hardcover
382 Pages

Dimensions(cm)
26.0 x 18.3 x 2.5

Hardcover

RRP $149.95

$148.75

or 4 interest-free payments of $37.19 with

Ships in 5 to 7 business days

This book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order super-scalars.

It discusses topics such as - the policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers - optimisations for high performance such as branch predictors, instruction scheduling, and load-store speculations - design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors - state-of-the-art multi threading and multiprocessing emphasising single chip implementations.

Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realisation. The emphasis is on how things work at a black box and algorithmic level.

The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.

About the Author

Jean-Loup Baer is Professor Emeritus of Computer Science and Engineering at the University of Washington, where he has been since 1969. Professor Baer is the author of Computer Systems Architecture and more than 100 refereed papers. He is a Guggenheim Fellow, an ACM Fellow, and an IEEE Fellow. Baer has held several editorial positions, including editor-in-chief of the Journal of VLSI and Computer Systems and editor of the IEEE Transactions on Computers, the IEEE Transactions on Parallel and Distributed Systems, and the Journal of Parallel and Distributed Computing. He has served as General Chair and Program Chair of several conferences, including ISCA and HPCA.

Industry Reviews

'The book gives a comprehensive and profound description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalers ... The book is very well structured with good presentation of the material. Each chapter finishes with many exercises, examples and additional literature. All the references are very up-to-date. As a conclusion I warmly recommend this book as a textbook for a course or just as a reference book.' Zentralblatt MATH

Shipping

	Standard Shipping	Express Shipping
Metro postcodes:	$9.99	$14.95
Regional postcodes:	$9.99	$14.95
Rural postcodes:	$9.99	$14.95

Orders over $79.00 qualify for free shipping.

How to return your order

At Booktopia, we offer hassle-free returns in accordance with our returns policy. If you wish to return an item, please get in touch with Booktopia Customer Care.

Additional postage charges may be applicable.

Defective items

If there is a problem with any of the items received for your order then the Booktopia Customer Care team is ready to assist you.

For more info please visit our Help Centre.

You Can Find This Book In

Non-Fiction Computing & I.T.Computer Science Computer Architecture & Logic Design Engineering & Technology Electronics & Communications Engineering Electronics Engineering Electronic Devices & Materials Microprocessors

Preface	p. xi
Introduction	p. 1
A Quick View of Technological Advances	p. 2
Performance Metrics	p. 6
Performance Evaluation	p. 12
Summary	p. 22
Further Reading and Bibliographical Notes	p. 23
Exercises	p. 24
References	p. 28
The Basics	p. 29
Pipelining	p. 29
Caches	p. 46
Virtual Memory and Paging	p. 59
Summary	p. 68
Further Reading and Bibliographical Notes	p. 68
Exercises	p. 69
References	p. 73
Superscalar Processors	p. 75
From Scalar to Superscalar Processors	p. 75
Overview of the Instruction Pipeline of the DEC Alpha 21164	p. 78
Introducing Register Renaming, Reorder Buffer, and Reservation Stations	p. 89
Overview of the Pentium P6 Microarchitecture	p. 102
VLIW/EPIC Processors	p. 111
Summary	p. 121
Further Reading and Bibliographical Notes	p. 122
Exercises	p. 124
References	p. 126
Front-End: Branch Prediction, Instruction Fetching, and Register Renaming	p. 129
Branch Prediction	p. 130
Sidebar: The DEC Alpha 21264 Branch Predictor	p. 157
Instruction Fetching	p. 158
Decoding	p. 164
Register Renaming (a Second Look)	p. 165
Summary	p. 170
Further Reading and Bibliographical Notes	p. 170
Exercises	p. 171
Programming Projects	p. 174
References	p. 174
Back-End: Instruction Scheduling, Memory Access Instructions, and Clusters	p. 177
Instruction Issue and Scheduling (Wakeup and Select)	p. 178
Memory-Accessing Instructions	p. 184
Back-End Optimizations	p. 195
Summary	p. 203
Further Reading and Bibliographical Notes	p. 204
Exercises	p. 205
Programming Project	p. 206
References	p. 206
The Cache Hierarchy	p. 208
Improving Access to L1 Caches	p. 209
Hiding Memory Latencies	p. 218
Design Issues for Large Higher-Level Caches	p. 232
Main Memory	p. 245
Summary	p. 253
Further Reading and Bibliographical Notes	p. 254
Exercises	p. 255
Programming Projects	p. 257
References	p. 258
Multiprocessors	p. 260
Multiprocessor Organization	p. 261
Cache Coherence	p. 269
Synchronization	p. 281
Relaxed Memory Models	p. 290
Multimedia Instruction Set Extensions	p. 294
Summary	p. 296
Further Reading and Bibliographical Notes	p. 297
Exercises	p. 298
References	p. 300
Multithreading and (Chip) Multiprocessing	p. 303
Single-Processor Multithreading	p. 304
General-Purpose Multithreaded Chip Multiprocessors	p. 318
Special-Purpose Multithreaded Chip Multiprocessors	p. 324
Summary	p. 330
Further Reading and Bibliographical Notes	p. 331
Exercises	p. 332
References	p. 333
Current Limitations and Future Challenges	p. 335
Power and Thermal Management	p. 336
Technological Limitations: Wire Delays and Pipeline Depths	p. 343
Challenges for Chip Multiprocessors	p. 346
Summary	p. 348
Further Reading and Bibliographical Notes	p. 349
References	p. 349
Bibliography	p. 351
Index	p. 361

Microprocessor Architecture

From Simple Pipelines to Chip Multiprocessors

At a Glance

Hardcover

Industry Reviews

Shipping

How to return your order

Defective items

You Can Find This Book In

More in Computer Architecture & Logic Design

Parallel Computing

Design and Analysis of Algorithms

Computer Architecture

A Modern Approach

Basic Computer Architecture

Fundamentals of Software Architecture

A Modern Engineering Approach

Making Embedded Systems

2nd Edition - Design Patterns for Great Software

Developing Graphics Frameworks with Java and OpenGL

Architecture Patterns with Python

Enabling Test-Driven Development, Domain-Driven Design, and Event-Driven Microservices

The Software Architect Elevator

Redefining the Architect's Role in the Digital Enterprise

Rust Atomics and Locks

Low-Level Concurrency in Practice

Clean Architecture

A Craftsman's Guide to Software Structure and Design

Domain-Driven Transformation

Modernize Legacy Systems and Mitigate Risk

Simply AI

Facts Made Fast

Learning Microsoft Power Automate

Improving Productivity for Business Processes and Workflows

Platform Engineering

A Guide for Technical, Product, and People Leaders

Learning Systems Thinking

Essential Non-Linear Skills and Practices for Software Professionals

Kubernetes - Up and Running

Dive into the Future of Infrastructure

AI Systems Performance Engineering

Optimizing Model Training and Inference Workloads with Gpus, Cuda, and Pytorch

Technology Strategy Patterns

Analyzing and Communicating Architectural Decisions

Fundamentals of DevOps and Software Delivery

A Hands-On Guide to Deploying and Managing Software in Production

Digital Design and Computer Architecture

ARM Edition

Beyond The Invisible Nexus

Dark Web, Dark AI and Offensive Security

Beyond The Invisible Nexus

Dark Web, Dark AI and Offensive Security

Modern Benford's Law

State of the Art Techniques for Audit and Compliance Professionals

Modern Benford's Law

State of the Art Techniques for Audit and Compliance Professionals

This product is categorised by