The Springer International Engineering and Computer Science

By: Gyungho Lee, Pen-Chung Yew, Lee Gyungho Lee (Editor)

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Hardcover | 31 July 2001

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Hardcover
164 Pages

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23.5 x 15.88 x 1.27

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Effective compilers allow for a more efficient execution of application programs for a given computer architecture, while well-conceived architectural features can support more effective compiler optimization techniques. A well thought-out strategy of trade-offs between compilers and computer architectures is the key to the successful designing of highly efficient and effective computer systems. From embedded micro-controllers to large-scale multiprocessor systems, it is important to understand the interaction between compilers and computer architectures.
The goal of the Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT) is to promote new ideas and to present recent developments in compiler techniques and computer architectures that enhance each other's capabilities and performance. Interaction Between Compilers and Computer Architectures is an updated and revised volume consisting of seven papers originally presented at the Fifth Workshop on Interaction between Compilers and Computer Architectures (INTERACT-5), which was held in conjunction with the IEEE HPCA-7 in Monterrey, Mexico in 2001. This volume explores recent developments and ideas for better integration of the interaction between compilers and computer architectures in designing modern processors and computer systems.
Interaction Between Compilers and Computer Architectures is suitable as a secondary text for a graduate level course, and as a reference for researchers and practitioners in industry.

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Non-Fiction Computing & I.T.Computer Science Computer Architecture & Logic Design Computer Programming & Software Development Compilers & Interpreters Computer Networking & Communications Systems Analysis & Design Computer Hardware Programming & Scripting Languages Software Engineering

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Published: 6th December 2010

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Preface	p. ix
EquiMax Optimal Scheduling Formulation	p. 1
Introduction	p. 1
Machine Description	p. 2
DAG Model	p. 4
Scheduling Problem	p. 5
Registers Constraints	p. 5
Resources Constraints	p. 6
Integer Linear Programming Techniques	p. 6
Writing Logical Operators with Linear Constraints	p. 7
Computing the Maximum with Linear Constraints	p. 9
EquiMax Integer Programming Formulation	p. 9
Scheduling Variables and Objective Function	p. 9
Registers Constraints	p. 10
Interference Graph	p. 10
Maximal Clique in the Interference Graph	p. 12
Resources Constraints	p. 13
Conflicting Graph	p. 13
Maximal Click in the Conflicting Graph	p. 14
Summary	p. 14
Related Work	p. 16
Conclusion	p. 18
An Efficient Semi-Hierarchical Array Layout	p. 21
Introduction	p. 22
Array Layout	p. 24
Linear Array Layouts	p. 24
Hierarchical Array Layouts	p. 25
Address Arithmetic	p. 25
Experimental Evaluation	p. 28
Cache Interference and Conflict Vectors	p. 29
Cache Interference	p. 29
Conflict Vectors	p. 32
Computing Conflict Vectors	p. 33
Self Interference	p. 35
Cross Interference	p. 36
Examples	p. 38
Related Work	p. 40
Conclusions	p. 40
Impact of Tile-Size Selection for Skewed Tiling	p. 45
Introduction	p. 45
Related Work	p. 47
Competing Tile-Size Selection Schemes	p. 47
Other Related Work	p. 48
Background	p. 49
Skewed Tiling	p. 49
Memory Hierarchy	p. 51
A Memory Cost Model	p. 51
Tile-Size Selection	p. 55
An Execution Cost Model for Tiling	p. 55
Tile-Size Selection Algorithm	p. 56
Preserving Property 1	p. 57
Preserving Property 2	p. 59
Algorithm STS	p. 60
A Running Example	p. 61
Experimental Evaluation	p. 62
Discussion	p. 65
Conclusion	p. 66
Improving Software Pipelining by Hiding Memory Latency	p. 69
Introduction	p. 70
Background	p. 71
Data-Reuse Analysis	p. 71
Software Pipelining	p. 73
Increased Register Requirements	p. 74
Previous Work	p. 74
A Motivating Example for Prefetching Loads	p. 75
Prefetching Loads	p. 77
Compiler Support for Identifying Candidates for Prefetching Loads	p. 77
Cache Design	p. 79
Experiment	p. 80
Initiation Interval	p. 82
Performance	p. 82
Register Pressure	p. 83
Conclusion	p. 84
Register Allocation for Embedded System	p. 89
Introduction	p. 90
Java exception and local variable consistency problem	p. 91
Partially fixed register allocation algorithm	p. 94
Experimental result	p. 96
Summary	p. 97
Is Compiling for Performance == Compiling for Power?	p. 101
Introduction	p. 101
Related Work	p. 103
Motivating Examples	p. 104
Compiler Optimizations	p. 106
Standard Optimization Levels	p. 106
Individual Optimizations	p. 107
Experimental Results	p. 108
Wattch 1.0 and Benchmarks	p. 108
Results	p. 109
Influence of Standard Optimizations on Energy	p. 109
Influence of Standard Optimizations on Power	p. 110
Influence of Individual Optimizations on Energy and Power	p. 111
Conclusions	p. 114
A Technology-Scalable Architecture for Fast Clocks and High ILP	p. 117
Introduction	p. 118
Architecture	p. 120
Computation Nodes	p. 120
Execution Model	p. 121
Instruction Mapping	p. 123
Instruction Wakeup and Execution	p. 124
Block Mapping	p. 125
Instruction Encoding	p. 125
Role of the Compiler	p. 126
Preliminary Analysis	p. 126
Instruction Behavior	p. 127
Block Size	p. 127
Grid Utilization	p. 130
Register Behavior	p. 131
Input, Output and Temporary Data	p. 131
Register fanout	p. 132
Technology Evaluation	p. 134
Related Work	p. 134
Conclusion	p. 136
Topic Index	p. 141
Author Index	p. 143
Table of Contents provided by Syndetics. All Rights Reserved.

The Springer International Engineering and Computer Science

At a Glance

Hardcover

Shipping

How to return your order

Defective items

You Can Find This Book In

Other Editions and Formats

Paperback

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