High-Level Power Analysis and Optimization

By: Anand Raghunathan, Niraj K. Jha, Sujit Dey

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Hardcover | 30 November 1997

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Hardcover
200 Pages

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24.77 x 16.51 x 1.91

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High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level.
High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power.
High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computing & I.T.Graphical & Digital Media Applications Computer-Aided Design CAD Energy Technology & Engineering Electrical Engineering

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Paperback

Published: 21st November 2012

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List of Figures
List of Tables
Preface
Introduction	p. 1
Low power design	p. 2
Design abstraction and levels of the design hierarchy	p. 5
Benefits of high-level power analysis and optimization	p. 12
Book overview	p. 15
Background	p. 17
Sources of power consumption	p. 18
Methods for reducing power and energy consumption	p. 22
High-level design techniques	p. 25
High-level synthesis application domains	p. 33
Architecture-Level Power Estimation	p. 37
Analytical power models	p. 38
Characterization based activity and power macromodels	p. 43
Power and switching activity estimation techniques for control logic	p. 67
Conclusions	p. 78
Power Management	p. 81
Clock-based power management: Gated and multiple clocks	p. 82
Pre-computation	p. 93
Scheduling to enable power management	p. 95
Operand isolation	p. 97
Power management through constrained register sharing	p. 102
Controller-based power management	p. 107
Conclusions	p. 114
High-Level Synthesis for Low Power	p. 115
Behavioral transformations	p. 116
Module selection	p. 126
Resource sharing	p. 129
Scheduling	p. 135
Supply voltage vs. switched capacitance trade-offs	p. 139
Optimizing memory power consumption during high-level synthesis	p. 142
Reducing glitching power consumption during high-level design	p. 145
Conclusions	p. 153
Conclusions and Future Work	p. 155
References	p. 159
Index	p. 173
Table of Contents provided by Blackwell. All Rights Reserved.

High-Level Power Analysis and Optimization

At a Glance

Hardcover

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Defective items

You Can Find This Book In

Other Editions and Formats

Paperback

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