Generating Hardware Assertion Checkers

1 Introduction. 1.1 Context and Motivation. 1.2 Book Objectives. 1.3 Overview of the Book. 1.4 External Contributions and Collaborations. 2 Assertions and the Verification Landscape. 2.1 Origins of Assertions: Software Checking. 2.2 Uses of Assertions in Hardware. 2.3 Assertion Checkers and Checker Generators. 2.4 Assertion Support in Simulators and Emulators. 2.5 Checkers in Silicon Debugging. 2.6 Assertions in Static and Dynamic Verification. 2.7 Supported Simulation and Emulation Semantics. 3 Basic Techniques Behind Assertion Checkers. 3.1 Background. 3.2 Modular Approach to Checker Generation. 3.3 Automata-Based Approach to Checker Generation. 3.4 Other Related Research. 4 PSL and SVA Assertion Languages. 4.1 The Property Specification Language. 4.2 SystemVerilog Assertions. 5 Automata for Assertion Checkers. 5.1 Introduction and Overview. 5.2 Automaton Framework. 5.3 Generating Circuit-Level Checkers from Assertion Automata. 6 Construction of PSL Assertion Checkers. 6.1 Introduction and Overview. 6.2 Automata Construction for Booleans. 6.3 Automata Construction for Sequences. 6.4 Automata Construction for Properties. 6.5 Automata Construction for Verification Directives. 7 Enhanced Features and Uses of PSL Checkers. 7.1 Introduction and Overview. 7.2 Recursive Compilation Strategies. 7.3 A Special Case for eventually! 7.4 Debug Enhancements for Checkers. 7.5 Checkers in Silicon Debug and On-Line Monitoring. 8 Evaluating and Verifying PSL Assertion Checkers. 8.1 Introduction and Overview. 8.2 Non-Synthetic Assertions. 8.3 Evaluating Assertion Grouping. 8.4 Pre-Synthesis Results. 8.5 Benchmarking Debug Enhancements. 8.6 Benchmarking Sequences and Properties. 9 Checkers for SystemVerilog Assertions. 9.1 Introduction and Overview. 9.2 Checker Generation for SystemVerilog Assertions. 9.3 Experimental Results for SVA Checkers. 10 Conclusions and FutureWork. 10.1 Conclusion. 10.2 FutureWork. A Example for Up-down Counter. References. Index.