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Functional Verification of Programmable Embedded Architectures

A Top-Down Approach

By: Prabhat Mishra, Nikil D. Dutt

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Paperback | 1 August 2005

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202 Pages

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23.5 x 16.51 x 1.91

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It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult to guarantee functional correctness at the system level under all possible operational scenarios. The problem is exacerbated in current System-on-Chip (SOC) design meth- ologies that employ Intellectual Property (IP) blocks composed of processor cores, coprocessors, and memory subsystems. Functional verification becomes one of the major bottlenecks in the design of such systems.

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computing & I.T.Computer Science Computer Architecture & Logic Design Systems Analysis & Design Information Technology General Issue Artificial Intelligence Expert Systems & Knowledge-Based Systems

Energy Technology & Engineering Electrical Engineering Digital Lifestyle & Online World: Consumer & User Guides Portable & Handheld Devices User Guides Graphical & Digital Media Applications Computer-Aided Design CAD

Introduction	p. 3
Architecture specification	p. 15
Validation of specification	p. 29
Executable model generation	p. 65
Design validation	p. 83
Functional test generation	p. 95
Conclusions	p. 121
Survey of contemporary ADLs	p. 127
Specification of DLX processor	p. 141
Interrupts & exceptions in ADL	p. 147
Validation of DLX specification	p. 151
Design space exploration	p. 155
Table of Contents provided by Blackwell. All Rights Reserved.

Functional Verification of Programmable Embedded Architectures

A Top-Down Approach

At a Glance

Paperback

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How to return your order

Defective items

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