| Preface | p. xiii |
| Introduction to Digital IC Testing | p. 1 |
| Introduction | p. 1 |
| Testing Problem and Considerations | p. 2 |
| Computational Complexity of Testing Problem | p. 3 |
| Estimation of Difficulty in Controllability and Observability | p. 4 |
| Summary | p. 8 |
| Problems | p. 8 |
| p. 8 |
| Faults in Digital Circuits | p. 9 |
| Introduction | p. 9 |
| General VLSI Fault Models | p. 10 |
| Stuck-at Fault Model | p. 10 |
| Bridging and Open Fault Model | p. 11 |
| Fault Equivalence, Dominance, and Collapsing | p. 13 |
| Parametric and Transient Faults | p. 14 |
| Delay Fault Models | p. 14 |
| Specific Fault Models | p. 15 |
| PLA Fault Model | p. 15 |
| Memory Fault Model | p. 16 |
| Microprocessor Fault Model | p. 17 |
| Summary | p. 18 |
| Problems | p. 18 |
| References | p. 19 |
| Bridging Faults in Random Logic | p. 21 |
| Introduction | p. 21 |
| Characterization of Bridging Faults | p. 21 |
| Bridging within a Logic Element | p. 22 |
| Bridging of Logical Nodes without Feedback | p. 25 |
| Bridging of Logical Nodes with Feedback | p. 33 |
| Bridging in Dynamic Gates | p. 37 |
| CMOS Domino Logic | p. 38 |
| Cascade Voltage Switch Logic | p. 40 |
| Clocked CMOS Logic | p. 40 |
| Effect of Substrate Connection | p. 42 |
| Summary | p. 49 |
| Problems | p. 50 |
| References | p. 51 |
| Open Faults in Random Logic | p. 53 |
| Introduction | p. 53 |
| Modeling of Open Faults | p. 53 |
| Problems in Testing Open Faults | p. 55 |
| Test Invalidation by Timing Skews | p. 55 |
| Test Invalidation by Charge Distribution | p. 57 |
| Test Invalidation Due to Glitches | p. 57 |
| Methods to Test Stuck-Open Faults | p. 59 |
| Robust Test Sequences | p. 59 |
| Testable Designs | p. 60 |
| Testability of Dynamic Circuits | p. 67 |
| Summary | p. 68 |
| Problems | p. 68 |
| References | p. 69 |
| Test Generation and Fault Simulation | p. 71 |
| Introduction | p. 71 |
| Test Generation at Gate Level | p. 71 |
| Boolean Difference Method | p. 72 |
| Path Sensitization and D-Algorithm | p. 75 |
| Algorithm PODEM | p. 78 |
| Algorithm FAN | p. 79 |
| Fault Coverage by a Test | p. 82 |
| Critical Path Tracing | p. 83 |
| Multiple Faults | p. 87 |
| Random Test Generation | p. 89 |
| Test Generation at Switch Level | p. 93 |
| Fault Simulation | p. 96 |
| Summary | p. 98 |
| Problems | p. 99 |
| References | p. 99 |
| Testing of Structured Designs (PLAs) | p. 101 |
| Introduction | p. 101 |
| Structure of a PLA | p. 101 |
| Easily Testable PLA | p. 105 |
| PLA Testing with Parity Trees | p. 105 |
| Universal Test Set for Easily Testable PLAs | p. 106 |
| Variations of Parity-Based Testable Design | p. 109 |
| Built-in Self-Test PLA | p. 111 |
| Testing of EEPLA | p. 111 |
| Testing for Multiple Faults in PLA | p. 116 |
| Fault Isolation and Reconfiguration | p. 119 |
| Summary | p. 120 |
| Problems | p. 122 |
| References | p. 122 |
| Testing of Random Access Memory | p. 123 |
| Introduction | p. 123 |
| Test Algorithms | p. 123 |
| Algorithm GALPAT | p. 124 |
| Checker Pattern Test | p. 124 |
| Galloping Diagonal/Row/Column Test | p. 125 |
| Marching 1/0 Test Algorithm | p. 126 |
| Modified Marching 1/0 Test | p. 126 |
| Comparison and Modification for Word-Oriented Memory | p. 127 |
| Testable Designs | p. 129 |
| BIST Memory | p. 130 |
| Memory Partitioning Methods | p. 131 |
| STD Architecture | p. 134 |
| Fault Diagnosis and Reconfiguration | p. 138 |
| Advantages and Disadvantages | p. 139 |
| Summary | p. 142 |
| Problems | p. 142 |
| References | p. 143 |
| Testing of Sequential Circuits | p. 145 |
| Introduction | p. 145 |
| Testing Problem in Sequential Circuits | p. 145 |
| State Table Approach | p. 146 |
| Initialization of Sequential Circuits | p. 146 |
| State Table Verification | p. 151 |
| Gate Level Test Generation Methods | p. 152 |
| Sequential Test Generation by Boolean Difference | p. 153 |
| Iterative Logic Array Model | p. 155 |
| Simulation-Based Test Generation | p. 164 |
| Divide and Conquer | p. 166 |
| Synthesis for Testability | p. 170 |
| Summary | p. 171 |
| Problems | p. 172 |
| References | p. 173 |
| Microprocessor Testing | p. 175 |
| Introduction | p. 175 |
| Microprocessor Description and Testing | p. 175 |
| Instruction Set Verification | p. 176 |
| Machine-Level Verification | p. 176 |
| Microinstruction-Level Verification | p. 182 |
| Bit-Sliced Microprocessors | p. 186 |
| Testing of One-Bit Slice | p. 187 |
| Testing of k-Bit Processor | p. 189 |
| Concurrent Checking | p. 191 |
| Error-Detecting Codes | p. 192 |
| Check-Point Technique | p. 192 |
| Watchdog Processor | p. 194 |
| Summary | p. 194 |
| References | p. 195 |
| Design for Testability | p. 197 |
| Introduction | p. 197 |
| SCAN Design | p. 197 |
| Multiplexed Data Scan Design | p. 198 |
| Level Sensitive Scan Design | p. 200 |
| Pros and Cons | p. 203 |
| Partial SCAN | p. 204 |
| Boundary SCAN | p. 207 |
| Basic Concept | p. 207 |
| Test Access Port | p. 209 |
| Cross-Check Design | p. 212 |
| Built-in Self-Test | p. 216 |
| Test Pattern Generators | p. 217 |
| Deterministic Test Pattern Generators | p. 217 |
| Pseudorandom Test Vectors | p. 217 |
| Pseudoexhaustive | p. 222 |
| Response Compression for BIST | p. 223 |
| Parity Testing | p. 224 |
| One-Count Testing | p. 224 |
| Syndrome Testing | p. 225 |
| Transition Count | p. 226 |
| Signature Analysis | p. 227 |
| BIST Test Structures | p. 232 |
| Built-in Logic Block Observer (BILBO) | p. 232 |
| Self-Test Using MISRs and Parallel SRSGs (STUMPS) | p. 233 |
| Circular Self-Test Path | p. 234 |
| Summary | p. 235 |
| Problems | p. 236 |
| References | p. 237 |
| Current Testing | p. 239 |
| Introduction | p. 239 |
| Basic Concept | p. 239 |
| Estimation of Fault-Free Current | p. 244 |
| Current Through a Single Gate | p. 244 |
| Estimation of Current in a Circuit | p. 247 |
| Current Sensing Techniques | p. 249 |
| External Current Sensor | p. 249 |
| Built-in Current Sensor | p. 252 |
| Test Generation for IDDQ Testing | p. 254 |
| Summary | p. 257 |
| Problems | p. 260 |
| References | p. 260 |
| Reliability Testing | p. 263 |
| Introduction | p. 263 |
| Component Quality and Fault Coverage | p. 264 |
| Reliability and Failure Rate | p. 265 |
| Failure Mechanisms | p. 269 |
| Chip Related Failures | p. 269 |
| Assembly Related Failures | p. 271 |
| Operation Induced Failures | p. 273 |
| Application Induced Failures | p. 279 |
| Reliability Test Methods | p. 281 |
| Accelerated Reliability Testing | p. 282 |
| Temperature Acceleration | p. 285 |
| Current Acceleration | p. 287 |
| Voltage Acceleration | p. 288 |
| Temperature-Humidity Acceleration | p. 290 |
| Vibration and Shock Acceleration | p. 291 |
| Temperature, Humidity, and Power Cycling | p. 291 |
| Burn-in | p. 292 |
| Testing of Application Induced Failures | p. 293 |
| Summary | p. 294 |
| Problems | p. 294 |
| References | p. 294 |
| Appendix A | p. 297 |
| Error Models | p. 297 |
| Computation of Aliasing Probability | p. 298 |
| Annotated Bibliography | p. 303 |
| Index | p. 311 |
| Table of Contents provided by Syndetics. All Rights Reserved. |
