Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

By: Manoj Sachdev, Jose Pineda de Gyvez

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Hardcover | 4 June 2007 | Edition Number 2

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Hardcover
352 Pages

Edition Type
Revised

Dimensions(cm)
23.5 x 15.88 x 1.91

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Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts.

The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Technology in General Technical Design Energy Technology & Engineering Electrical Engineering

Dedication	p. v
Preface	p. xiii
Foreword	p. xvii
Foreword for the First Edition	p. xix
Acknowledgements	p. xxi
Introduction	p. 1
Evolution of CMOS Technology	p. 1
The Test Complexity	p. 5
Quality and Reliability Awareness	p. 9
Building Quality and Reliability	p. 11
Objectives of this Book	p. 15
Book Organization	p. 16
Functional and Parametric Defect Models	p. 23
Brief Classification of Defects	p. 23
Defect-Fault Relationship	p. 26
Induetieve Fault Analysis	p. 28
IC Design and Layout Related Defect Sensitivity	p. 29
Defect Sensitive Design	p. 29
Basic Concepts of IFA	p. 30
Parametric Defect and Fault Models	p. 32
Threshold Voltage Mismatch ([Delta]V[subscript t]) Fault Modeling	p. 32
Sources of Threshold Voltage Variability	p. 33
Leakage Current due to V[subscript t] Mismatch	p. 34
Delay in Parallel-connected Networks	p. 39
Delay Variation Model with [Delta]V[subscript t] for Parallel Transistor Networks	p. 41
Spot Defect Statistics: Resistive Opens	p. 45
Functional Defect Models	p. 50
Critical Areas	p. 53
Defect Statistics	p. 54
Average Probability of Failure of Long Interconnects	p. 58
Average Critical Area of N Conductors	p. 61
Conclusions	p. 64
Digital CMOS Fault Modeling	p. 69
Objectives of Fault Modeling	p. 69
Levels of Testing	p. 71
Levels of Fault Modeling	p. 73
Logic Level Fault Modeling	p. 73
Transistor Level Fault Modeling	p. 81
Layout Level Fault Modeling	p. 90
Function Level Fault Modeling	p. 91
Delay Fault Models	p. 92
Leakage Fault Model	p. 97
Temporary Faults	p. 98
Conclusions	p. 102
Defects in Logic Circuits and their Test Implications	p. 111
Introduction	p. 111
Stuck-at Faults and Manufacturing Defects	p. 113
Study by Galiay, Crouzet and Vergniault	p. 114
Study by Banerjee and Abraham	p. 115
Study by Maly, Ferguson and Shen	p. 120
Gate Oxide Shorts: Study by Hawkins and Soden	p. 123
IFA Experiments on Standard Cells	p. 126
I[subscript DDQ] versus Voltage Testing	p. 130
Defects in Sequential Circuits	p. 133
Undetected Defects	p. 135
Defect Detection Technique	p. 137
I[subscript DDQ] Testable Flip-flop	p. 139
Defects and Scan Chains	p. 139
Defect Classes and their Testing	p. 143
Application of IFA in Nano-metric Technologies	p. 143
Conclusions	p. 146
Testing Defects and Parametric Variations in RAMs	p. 151
Introduction	p. 151
Traditional RAM Fault Models	p. 153
Stuck-at Fault Model	p. 153
Coupling Fault Model	p. 154
Pattern Sensitivity Fault Model	p. 154
Defect Based RAM Fault Model Development	p. 155
Defect based SRAM Fault Models and Test Algorithms	p. 155
Subsequent Defect-oriented SRAM Test Development	p. 160
Defect based DRAM Fault Models and Test Algorithms	p. 163
TCAM Fault Models and Test Algorithms	p. 176
Address Decoder Defects	p. 185
Early Work on Address Decoder Faults	p. 187
Technological Differences	p. 187
Failure and Analysis	p. 189
Why Non-detection by March Tests?	p. 192
Address Decoder Open Defects	p. 193
Supplementary Test Algorithm	p. 195
Testability Techniques for Decoder Open Defects	p. 197
Recent Work on Address Decoder Defects	p. 200
Parametric Testing of SRAMs	p. 200
SRAM Cell and SNM	p. 203
Process Variation and SNM	p. 207
Manufacturing Defects and SNM	p. 209
Weak Cell Fault Model	p. 210
DfT Techniques to Detect Weak Cells	p. 211
I[subscript DDQ] Based RAM Testing	p. 215
Conclusions	p. 215
Defect-oriented Analog Testing	p. 225
Introduction	p. 226
Analog Test Complexity	p. 227
Previous Work	p. 228
Estimation Method	p. 228
Topological Method	p. 228
Taxonomical Method	p. 230
Defect Based Realistic Fault Dictionary	p. 230
Implementation	p. 234
A Case Study	p. 240
Fault Matrix Generation	p. 240
Stimuli Matrix	p. 242
Simulation Results	p. 243
Silicon Results	p. 244
Observations and Analysis	p. 248
IFA: Strengths and Weaknesses	p. 249
Input Stimuli Generation	p. 251
Power Supply Ramp Input Test Stimuli	p. 252
Amplifier Specs	p. 254
Structural vs. Functional Fault Coverage	p. 259
Experimental Results	p. 264
IFA Based Fault Grading and DfT for Analog Circuits	p. 268
A/D Converter Testing	p. 268
Description of the Experiment	p. 269
Fault Simulation Issues	p. 270
Fault Simulation Results	p. 272
High Level Analog Fault Models	p. 278
Conclusions	p. 281
Yield Engineering	p. 289
Mathematical Models for Yield Prediction	p. 289
Layout Oriented Yield Prediction	p. 300
Yield Engineering	p. 301
Economics and Yield Forecasting	p. 306
Conclusions	p. 312
Conclusion	p. 317
Test and Yield Engineering Complexity in Nano-metric Technologies	p. 317
Role of Defect-oriented Testing	p. 320
Strengths of Defect-oriented Testing	p. 320
Limitations of Defect-oriented Testing	p. 321
Future Directions	p. 321
Index	p. 325
Table of Contents provided by Ingram. All Rights Reserved.

Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

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