CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

Process-Aware SRAM Design and Test

By: Andrei Pavlov, Manoj Sachdev

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Hardcover | 21 June 2008

At a Glance

Hardcover
212 Pages

Dimensions(cm)
23.5 x 15.88 x 1.27

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CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

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You Can Find This Book In

Non-Fiction Engineering & Technology Technology in General Nanotechnology Electronics & Communications Engineering Electronics Engineering Electronic Devices & Materials Semi-Conductors & Super-Conductors Computing & I.T.Computer Hardware Circuits & Components Computer Science

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Paperback

Published: 28th October 2010

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Introduction and Motivation	p. 1
SRAM Circuit Design and Operation	p. 13
SRAM Cell Stability: Definition, Modeling and Testing	p. 39
Traditional SRAM Fault Models and Test Practices	p. 79
Techniques for Detection of SRAM Cells with Stability Faults	p. 103
Soft Errors in SRAMs: Sources, Mechanisms, and Mitigation Techniques	p. 159
References	p. 183
Index	p. 191
Table of Contents provided by Blackwell. All Rights Reserved.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

Process-Aware SRAM Design and Test

At a Glance

Hardcover

Shipping

How to return your order

Defective items

You Can Find This Book In

Other Editions and Formats

Paperback

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