Behavioral Intervals in Embedded Software : Timing and Power Analysis of Embedded Real-Time Software Processes - Fabian Wolf

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Behavioral Intervals in Embedded Software

Timing and Power Analysis of Embedded Real-Time Software Processes

By: Fabian Wolf

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Hardcover | 31 July 2002 | Edition Number 2

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Hardcover
216 Pages

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23.5 x 15.88 x 0.64

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This title introduces a comprehensive approach to timing, power, and communication analysis of embedded software processes. Embedded software timing, power and communication are typically not unique but occur in intervals which result from data dependent behaviour, environment timing and target system properties. In system design, these intervals are used in many ways. In some cases, only the worst case is of interest, for example, for single processor schedulability analysis, whereas in another context both best and worst cases are relevant, such as for multiprocessor scheduling. In all these cases, these behavioural intervals of the individual software processes are fundamental data needed to analyze system behaviour. With growing importance of embedded software, formal analysis of behavioural intervals has met increasing interest. While all approaches are conservative, that is, all possible timing behaviour (or communication, power consumption) is included in the resulting intervals, the main differences are in the architecture features that are covered by the hardware model and the width of the conservative interval. The closer this interval to the real timing bounds, the higher is the practical use of formal analysis. Analysis techniques leverage on previous work in compiler technology by using basic blocks as elementary units for architecture modelling and path analysis. The work presented here offers an alternative direction, moving from basic block-based analysis to an analysis based on larger program segments with a single execution path.

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You Can Find This Book In

Non-Fiction Computing & I.T.Computer Programming & Software Development Software Engineering Software Testing & Verification Engineering & Technology Electronics & Communications Engineering Electronics Engineering Computer Science Systems Analysis & Design Graphical & Digital Media Applications Computer-Aided Design CAD

Artificial Intelligence Expert Systems & Knowledge-Based Systems Civil Engineering Building Construction & Materials Security & Fire Alarm Systems Computer Architecture & Logic Design

List of Figures	p. xi
List of Tables	p. xv
Foreword	p. xvii
Preface	p. xix
Abstract	p. xxi
Introduction	p. 1
Embedded Real-Time Systems	p. 1
Software Performance Estimation	p. 3
Application Domains	p. 6
Codesign of Embedded Real-Time Systems	p. 6
Global System Representation	p. 6
System Design	p. 6
Summary and Problem Identification	p. 7
Proposed Solution	p. 7
Software Running Time Analysis	p. 9
General Requirements and Background	p. 9
Process Model	p. 9
Influences on Process Running Time	p. 10
Input Data and Parameters	p. 11
Input Data Dependent Control Flow	p. 11
Input Data Dependent Instruction Execution	p. 12
Program Simulation and Test Patterns	p. 12
Static Program Analysis	p. 12
Path Identification	p. 13
Annotations Using a Timing Analysis Language	p. 13
Source Level Timing Scheme	p. 14
Path Annotation Using Regular Expressions	p. 15
Implicit Path Enumeration and Cost Model	p. 15
Functional Constraints	p. 15
Structural Constraints and Solution	p. 16
Overlapping Basic Block Execution	p. 17
Limitations and Possible Extensions	p. 18
Other Previous Work	p. 18
Branching Probabilities	p. 18
Test Patterns Generation	p. 19
Data Flow Frameworks	p. 20
Abstract Interpretation	p. 20
Automatic Loop Bounding	p. 21
Symbolic Extension to Simulators	p. 21
Source Level Timing Annotations	p. 22
Real Time Euclid	p. 22
Spark Proof and Timing System	p. 23
The SYMTA Approach to Path Analysis	p. 23
Hybrid Analysis	p. 23
Local Cost Model	p. 24
Informal Path Classification	p. 25
SFP Identification and Path Clustering	p. 26
Calculation of Global Cost	p. 29
Limitations	p. 29
A Formal Approach to Symta	p. 31
Syntax Graph	p. 31
Classification of Program Segments	p. 32
Program Segment Cost	p. 35
Validation of the Approach	p. 36
Proof of Conservativity	p. 36
Transition Cost	p. 38
Functional and Structural Constraints	p. 39
Function Calls	p. 39
Exploitation	p. 40
Example: Bubble Sort	p. 40
Path Analysis	p. 41
Global Cost Calculation	p. 42
Limitations	p. 43
Hierarchical Control Flow Graph	p. 43
Context Dependent Execution	p. 44
ATM Switch Component	p. 44
Context Dependent Execution Cost	p. 46
Context Dependency in Array Elements	p. 46
Example: Integration of Context Dependent Paths	p. 48
Conclusion	p. 50
Formal Cache Analysis in Symta	p. 51
Motivation and Background	p. 51
Cache Properties	p. 52
Cache and Memory Architecture	p. 52
Instruction and Data Cache	p. 52
Set Associativity	p. 53
Previous Work on Cache Analysis	p. 54
Trace Based Cache Simulation	p. 54
First Hit/Miss Scenario	p. 55
Cache State Transition Graph	p. 55
Clustering in the Cache Conflict Graph	p. 60
Use-/Define Chains for Data Access Addresses	p. 61
Static Categorization of Cache Accesses	p. 61
Pipeline and Cache States	p. 63
Abstract Interpretation	p. 63
Straight-Line Code Programs	p. 65
Local Program Segment Simulation	p. 65
Program Properties Found by SYMTA	p. 65
Access Addresses and Data Caches	p. 66
Local Simulation	p. 66
Program Segment Cache Evaluation	p. 67
Data Flow Analysis for Cache Sets	p. 68
Cache Set Content Prediction	p. 69
Hybrid Prediction Approach	p. 70
Evaluation of Flow Analysis Results	p. 71
Process-Level Cost Calculation	p. 72
Cache Modeling and Representation	p. 73
Application of Cache Constraints	p. 73
Impact on Execution Cost	p. 74
Process Preemptions	p. 75
Examples for Cache Analysis	p. 76
Direct Mapped Cache Analysis	p. 76
Set Associative Cache Analysis	p. 78
Conclusion	p. 82
Program Segment Cost Analysis	p. 83
Processor Simulators	p. 83
Previous Work in Processor Simulation	p. 83
Instruction Cost Addition ICA	p. 84
Extensions to ICA	p. 85
Program Segment Simulation PSS	p. 85
Implemented Simulators	p. 87
Simulator Interfaces	p. 88
Segment-Wise Simulation Methodology	p. 89
Simulation of the Complete Program Code	p. 89
Simulation of Isolated Program Segments	p. 89
Open Interface to Code Instrumentation	p. 90
Modeling Shared Resources	p. 92
Context Switch	p. 92
Scheduling Strategies	p. 93
Behavioral Intervals for Process Sequences	p. 94
Interrupts	p. 94
Execution Cost Measurement	p. 95
Motivation and Problem Identification	p. 96
Previous Work on Measurement	p. 96
Segment-Wise Timing and Power Measurement	p. 98
Compact Timed Trace Acquisition	p. 99
SPARClite Timing and Power Measurement	p. 100
Conclusion	p. 102
Experiments and Results	p. 103
Single Feasible Path Analysis	p. 103
Context Dependent Path Analysis	p. 104
Architecture Modeling by Simulation	p. 105
Impact of Trigger Point Insertion	p. 105
Local Cache Analysis	p. 107
Improvements to Basic Block Based Analysis	p. 108
SFP Analysis Without Functional Constraints	p. 108
Cache Parameters	p. 112
SFP Analysis With Functional Constraints	p. 112
ILP Problem Size	p. 113
Exploitation of Context Dependency	p. 114
Comparing Architectures	p. 116
OAM Component	p. 117
Case Study: Filter on Packet Data	p. 118
Detailed Power Analysis	p. 122
Instruction Energy Consumption Intervals	p. 123
Measurement of Instruction Sequences	p. 124
Instruction Cost Addition Evaluation	p. 126
Process-Level Energy Intervals	p. 126
Conclusion	p. 127
Summary and Conclusion	p. 129
Summary	p. 129
Conclusion	p. 130
Appendices	p. 131
System Implementation	p. 131
Overview	p. 131
Tool Flow	p. 132
SYMTA Designer Interface	p. 133
Path Analysis Software	p. 134
Symbolic Execution	p. 134
Process Mode Annotation	p. 134
Path Identification	p. 134
ILP Solution	p. 134
Cache Analysis Software	p. 135
Local Simulation	p. 135
Set Definition Propagation	p. 135
Future Work	p. 136
Architecture Modeling	p. 137
PSS: StrongARM Simulator	p. 137
Hardware Interfaces	p. 138
Communication Components	p. 138
Bus Controller	p. 138
Cache Simulation	p. 140
ICA: Data Book Implementation	p. 140
Software Power Analysis	p. 140
Power Measurement	p. 140
Instruction-Wise Power Analysis	p. 142
Example: SPARClite Power Measurement	p. 142
Further Implementation Details	p. 143
ICA for SPARClite Power Consumption	p. 148
Design Flow Integration in MEDIA	p. 148
System Property Intervals	p. 149
Generation of Experimental Results	p. 151
Path Analysis	p. 151
Symbolic Simulation	p. 151
ILP Solving	p. 151
Architecture Modeling	p. 151
StrongARM Simulation	p. 151
StrongARM Simulation Case Studies	p. 153
Measurement	p. 154
Measurement Case Study: Image Processing	p. 157
Intermediate Formats: Bubble Sort	p. 158
Source Code	p. 158
Symbolic Expressions	p. 159
Control Flow Graph	p. 159
ILP solver input	p. 161
Analysis Improvements in Previous Work	p. 161
Graphical Behavioral Interval Representation	p. 163
Abbreviations	p. 169
Biography	p. 171
Publications	p. 173
Bibliography	p. 175
Index	p. 187
Table of Contents provided by Ingram. All Rights Reserved.

Behavioral Intervals in Embedded Software

Timing and Power Analysis of Embedded Real-Time Software Processes

At a Glance

Hardcover

Shipping

How to return your order

Defective items

You Can Find This Book In

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