| Introduction | p. 1 |
| Low-voltage analog circuit design challenges | p. 4 |
| Opportunities at low voltages | p. 9 |
| Organization of the book | p. 14 |
| Fully Differential Operational Transconductance Amplifiers (OTAs) | p. 17 |
| Body-input OTA | p. 19 |
| Gate-input OTA | p. 23 |
| On-chip biasing circuits for the gate-input OTA | p. 29 |
| Error amplifier | p. 30 |
| Generating a fixed level shift | p. 31 |
| Setting the OTA output DC common-mode voltage | p. 32 |
| Gain enhancement | p. 33 |
| Start-up | p. 35 |
| Characterization results for the body-input and gate-input OTAs | p. 35 |
| Body-input OTA measurements | p. 35 |
| Gate-input OTA measurements | p. 36 |
| Discussion on the two OTA design techniques | p. 39 |
| Design methodology for low V[subscript T] devices, without body access | p. 41 |
| Fully differential OTA | p. 41 |
| Bias circuits | p. 45 |
| Summary | p. 45 |
| Weak Inversion MOS Varactors for Tunable Integrators | p. 49 |
| Brief theoretical overview | p. 50 |
| Device measurements and modeling | p. 50 |
| Closed-form model | p. 52 |
| Channel segmentation | p. 54 |
| Comparison between measured results and simulations | p. 56 |
| Circuit applications | p. 56 |
| Discrete prototype using the varactor | p. 56 |
| Application of the varactor in an integrated setting | p. 56 |
| Summary | p. 60 |
| A 0.5 V 5th-Order Low-Pass Elliptic Filter | p. 61 |
| Filter topology | p. 61 |
| On-chip PLL-based automatic frequency tuning loop | p. 62 |
| Layout and prototype chip | p. 65 |
| Characterization Results | p. 66 |
| Test set-up | p. 66 |
| Frequency response | p. 66 |
| Noise | p. 67 |
| Distortion and characterization over tuning range | p. 67 |
| Performance at different power supply voltages | p. 69 |
| Performance over different chips | p. 69 |
| Performance over temperature | p. 71 |
| Summary | p. 71 |
| A 0.5 V Track-and-Hold (T/H) Circuit | p. 77 |
| Introduction | p. 77 |
| T/H operation at ultra-low voltages | p. 77 |
| Fully-differential 0.5 V T/H circuit | p. 79 |
| Charge injection and sampling times | p. 80 |
| Fully-differential implementation | p. 81 |
| Common-mode rejection | p. 81 |
| Integrated noise | p. 83 |
| Track-and-hold test strategy | p. 86 |
| Design details and measurement results | p. 86 |
| Gate-input OTA | p. 86 |
| Switches | p. 87 |
| Clock generation | p. 87 |
| Prototype chip | p. 90 |
| Simulated performance | p. 91 |
| Measured performance | p. 91 |
| Conclusion | p. 92 |
| A 0.5 V Continuous-Time [Sigma Delta] Modulator | p. 97 |
| Introduction | p. 97 |
| Return-to-Open DAC | p. 98 |
| Similar DAC concepts | p. 99 |
| Noise improvements by RTO DAC | p. 102 |
| Return to Zero timing | p. 103 |
| Split RTO DAC Modulator Architecture | p. 103 |
| Modulator clocking | p. 104 |
| Modulator design | p. 105 |
| Values of R and C | p. 106 |
| Building Block Circuits for 0.5 V Supply | p. 108 |
| RTO DAC Circuit | p. 108 |
| Comparator | p. 110 |
| Operational transconductance amplifiers | p. 110 |
| Clock generation circuit | p. 112 |
| Experimental Results | p. 112 |
| Conclusions | p. 120 |
| 0.5 V Receiver Front-End Circuits | p. 121 |
| Introduction | p. 121 |
| RF Receiver System-Level Considerations | p. 121 |
| Low-Noise Amplifiers | p. 122 |
| Basic Properties and Standard Topologies | p. 122 |
| Low-Voltage Considerations | p. 123 |
| Downconversion Mixers | p. 124 |
| Basic Properties and Standard Topologies | p. 124 |
| Low-Voltage Considerations | p. 126 |
| 900 MHz Receiver Front-End in 0.18 [mu]m CMOS | p. 127 |
| Design of the LNA | p. 127 |
| Design of the downconversion mixer | p. 130 |
| Design of the LO buffers | p. 134 |
| Measurement and results | p. 135 |
| Analysis of a Distributed Model for a MOS Capacitor | p. 141 |
| References | p. 147 |
| Index | p. 155 |
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