| Foreword | p. xiii |
| Preface | p. xvii |
| Contributing Authors | p. xxiii |
| Dedication | p. xxv |
| Defect-Oriented Testing | p. 1 |
| History of Defect-Oriented Testing | p. 2 |
| Classic Defect Mechanisms | p. 4 |
| Shorts | p. 4 |
| Opens | p. 6 |
| Parametric Changes | p. 7 |
| Defect Mechanisms in Advanced Technologies | p. 8 |
| Copper-related Defects | p. 8 |
| Optical Defects | p. 10 |
| Design-related Defects | p. 12 |
| Defects and Faults | p. 14 |
| Uses of Fault Models | p. 15 |
| Single Stuck-at Faults | p. 16 |
| Bridging Faults | p. 17 |
| Open Fault Models | p. 22 |
| Timing-related or Delay Faults | p. 24 |
| I[subscript DDQ] Models | p. 27 |
| Defect-Oriented Test Types | p. 28 |
| Logic Tests | p. 28 |
| Current-based Tests | p. 29 |
| Delay Test | p. 31 |
| Very Low Voltage | p. 32 |
| Stress Testing | p. 33 |
| Experimental Results | p. 34 |
| Fault Coverage, Scan vs. Functional | p. 34 |
| Effectiveness of I[subscript DDQ], Scan, At-speed Tests | p. 34 |
| Statistical Post Processing | p. 39 |
| Future Trends and Conclusions | p. 39 |
| Acknowledgments | p. 40 |
| References | p. 40 |
| Failure Mechanisms and Testing in Nanometer Technologies | p. 43 |
| Scaling CMOS Technology | p. 44 |
| Device Scaling | p. 45 |
| Interconnect Scaling | p. 51 |
| Parameter Variations | p. 52 |
| Noise | p. 55 |
| Failure Modes in Nanometer Technologies | p. 57 |
| Bridge Defects | p. 57 |
| Open Circuit Defects | p. 60 |
| Parametric Failures | p. 61 |
| Test Methods for Nanometer ICs | p. 65 |
| Impact of Technology Scaling on Testing | p. 66 |
| Dealing with Background Current Increase | p. 67 |
| Noise-tolerant Techniques | p. 68 |
| Impact of Variation on Delay | p. 72 |
| Conclusion | p. 73 |
| References | p. 73 |
| Silicon Debug | p. 77 |
| Introduction | p. 77 |
| Silicon Debug History | p. 79 |
| Silicon Debug Process | p. 80 |
| Post-silicon Validation | p. 80 |
| Debug Flow | p. 82 |
| Step 1: Control the Failure | p. 82 |
| Step 2: Isolate the Failing Circuit | p. 84 |
| Step 3: Root Cause the Failure | p. 89 |
| Step 4: Try to Expand the Problem | p. 91 |
| Circuit Failures | p. 92 |
| Speedpaths | p. 92 |
| Mintime Races | p. 92 |
| Charge Sharing | p. 94 |
| Interconnect Noise | p. 96 |
| Leakage | p. 98 |
| Manufacturability | p. 100 |
| A Case Study in Silicon Debug | p. 101 |
| Future Challenges for Silicon Debug | p. 105 |
| Conclusion | p. 106 |
| Acknowledgements | p. 107 |
| References | p. 107 |
| Delay Testing | p. 109 |
| Introduction | p. 109 |
| Why Delay Testing | p. 109 |
| Why Now | p. 110 |
| Delay Test Basics | p. 110 |
| Transition Delay Basics | p. 114 |
| Path Delay Basics | p. 115 |
| Test Application | p. 116 |
| Scan Architectures | p. 116 |
| Last-Shift-Launch | p. 116 |
| System-Clock-Launch | p. 118 |
| Hybrid Launch | p. 119 |
| BIST and Delay Testing | p. 119 |
| Philosophy and Delay Test Application | p. 120 |
| Delay Test Details | p. 121 |
| Clock Domain Issues | p. 121 |
| I/O Issues | p. 124 |
| Vector Generation | p. 125 |
| Last-Shift-Launch | p. 126 |
| System-Clock-Launch | p. 126 |
| Fault Model Tweaks | p. 127 |
| Selecting Faults | p. 127 |
| Chip Design Constructs | p. 129 |
| Phase-Locked Loops (PLLs) | p. 129 |
| Core Test Support | p. 130 |
| I/O Loopback | p. 132 |
| ATE Requirements | p. 132 |
| I/O Requirements | p. 133 |
| Speed Requirements | p. 133 |
| Power Requirements | p. 135 |
| Conclusions: Tests vs. Defects | p. 136 |
| Acknowledgements | p. 137 |
| References | p. 137 |
| High-Speed Digital Test Interfaces | p. 141 |
| New Concepts | p. 141 |
| Introduction | p. 141 |
| Transmission Lines | p. 143 |
| Technology and Design Techniques | p. 151 |
| Parasitics Minimization | p. 151 |
| Loss Mitigation | p. 154 |
| Differential Signaling | p. 157 |
| Termination | p. 160 |
| Power Supply and Decoupling | p. 163 |
| Characterization and Modeling | p. 167 |
| Characterization Techniques | p. 168 |
| Path Modeling | p. 172 |
| Power Distribution System Modeling | p. 175 |
| Outlook | p. 176 |
| References | p. 177 |
| DFT-Oriented, Low-Cost Testers | p. 179 |
| Introduction | p. 180 |
| Historical Perspective on Structural Test | p. 182 |
| Test Cost - the Chicken and the Low Cost Tester | p. 184 |
| Schedule, Work Product, and Time-to-Market | p. 184 |
| Manufacturing Test Cost | p. 186 |
| Tester Use Models | p. 188 |
| Why and When is DFT Low Cost? | p. 190 |
| Functional vs. Structural Test | p. 190 |
| Structural Test, DFT, and Cost | p. 191 |
| Test Development Automation | p. 194 |
| Defect Coverage and Fault Models | p. 196 |
| DFT and First Silicon Validation | p. 199 |
| DFT and Device Characterization | p. 201 |
| DFT and Yield Learning | p. 203 |
| What does Low Cost have to do with the Tester? | p. 204 |
| What Makes a Tester Expensive? | p. 204 |
| Achieving Test Goals Without Precision, Accuracy, Flexibility | p. 207 |
| The Next Step in Test Cost Reduction - the Test Interface | p. 209 |
| The LCST is Not the Silver Bullet | p. 212 |
| Life, the Universe, and Everything | p. 213 |
| References | p. 215 |
| Recommended Reading | p. 216 |
| Embedded Cores and System-on-Chip Testing | p. 217 |
| Embedded Cores and SOCs | p. 218 |
| Design and Test Paradigm with Cores and SOCs | p. 219 |
| Classification and Use of Embedded Cores | p. 219 |
| Components of an SOC | p. 220 |
| DFT for Embedded Cores and SOCs | p. 222 |
| Conventional DFT Techniques | p. 222 |
| DFT for Embedded Cores | p. 223 |
| DFT for SOCs | p. 226 |
| Test Access Mechanisms | p. 228 |
| Test Interface Control Requirements | p. 228 |
| 1149.1 JTAG TAP Interface | p. 229 |
| IEEE 1500 Standard Test Interface | p. 230 |
| ATPG for Embedded Cores and SOCs | p. 232 |
| Limitations of Conventional ATPG | p. 232 |
| Use of Scan Models | p. 233 |
| SOC Test Coverage Estimation | p. 235 |
| SOC Test Modes | p. 236 |
| Role of Test Modes | p. 236 |
| Design and Categories of Test Modes | p. 237 |
| Test Pin Requirements | p. 239 |
| Test Mode Selection Mechanisms | p. 239 |
| Examples of Complex Test Modes | p. 240 |
| Design for At-speed Testing | p. 241 |
| Need for At-speed Testing | p. 241 |
| Requirements for SOC At-speed Test | p. 242 |
| Functional Tests for At-speed Testing | p. 243 |
| Scan Design and Scan Control | p. 244 |
| Clock Control for At-speed Testing | p. 244 |
| Handling Violating Paths | p. 246 |
| Test Control Through I/Os | p. 247 |
| Pattern Generation Techniques | p. 247 |
| Design for Memory and Logic BIST | p. 248 |
| BIST Overview | p. 248 |
| Design Techniques for Memory BIST | p. 249 |
| Design Techniques for Logic BIST | p. 252 |
| Functional BIST | p. 255 |
| SOC BIST Architecture | p. 257 |
| Conclusion | p. 257 |
| Acknowledgements | p. 259 |
| References | p. 259 |
| Embedded Memory Testing | p. 263 |
| Introduction | p. 263 |
| The Memory Design Under Test | p. 267 |
| Static Memory | p. 268 |
| Register Files | p. 271 |
| Dual Port Memories | p. 272 |
| Content Addressable Memories | p. 274 |
| Dynamic Random Access Memories | p. 274 |
| Memory Faults | p. 276 |
| Memory Test Patterns | p. 282 |
| Pattern Nomenclature | p. 283 |
| Key March Patterns | p. 284 |
| Memory Data Backgrounds | p. 287 |
| CAM Test Patterns | p. 289 |
| Self Test | p. 290 |
| Advanced Memories & Technologies | p. 295 |
| Conclusions | p. 298 |
| References | p. 298 |
| Mixed-Signal Testing and DfT | p. 301 |
| A Brief History | p. 302 |
| Functional vs. Structural Test | p. 303 |
| Testing | p. 304 |
| Design-for-Test | p. 305 |
| Fault Modeling | p. 307 |
| The State of the Art | p. 310 |
| Testing | p. 311 |
| DfT | p. 318 |
| Fault Modeling | p. 320 |
| Advances in the Last 10 Years | p. 321 |
| Testing | p. 322 |
| DfT | p. 323 |
| Fault Modeling | p. 329 |
| Emerging Techniques and Directions | p. 329 |
| Testing | p. 330 |
| DfT | p. 330 |
| EDA Tools for Mixed-Signal Testing | p. 331 |
| Testing | p. 331 |
| DfT | p. 332 |
| Fault Modeling | p. 332 |
| Future Directions | p. 332 |
| References | p. 334 |
| RF Testing | p. 337 |
| Introduction | p. 337 |
| Testing RF ICs | p. 339 |
| RF IC Categories | p. 339 |
| RF Test Challenges | p. 340 |
| RF Test Cost Reduction Factors | p. 341 |
| Resources and Test Time Cost | p. 342 |
| Handler | p. 344 |
| Test Hardware | p. 346 |
| Universal Test Board | p. 347 |
| RF Test Function Sub-Circuit Design | p. 348 |
| Complete Test Architecture | p. 353 |
| Hardware Development Process | p. 356 |
| High Frequency Simulation Tools | p. 359 |
| Schematic Simulation | p. 359 |
| 2.5D RF Board Simulation | p. 362 |
| 3D RF Socket and Package Modeling | p. 365 |
| Device Under Test Interface | p. 367 |
| Sockets | p. 367 |
| Wafer Probes | p. 367 |
| Conclusions | p. 368 |
| Acknowledgements | p. 368 |
| References | p. 368 |
| Loaded Board Testing | p. 371 |
| The Defect Space at Board Test | p. 372 |
| What is a "Defect"? | p. 372 |
| What is a "Fault"? | p. 373 |
| The "PCOLA/SOQ" Model | p. 374 |
| Test Coverage | p. 376 |
| In-Circuit Test (ICT) | p. 378 |
| Unpowered Shorts Tests | p. 380 |
| Unpowered Analog Tests | p. 384 |
| Powered In-Circuit Digital Tests | p. 391 |
| Boundary-Scan Tests | p. 394 |
| Powered Mixed-Signal Tests | p. 397 |
| Pros and Cons of ICT | p. 398 |
| Loaded Board Inspection Systems | p. 399 |
| Automatic Optical Inspection (AOI) | p. 400 |
| Automatic X-Ray Inspection (AXI) | p. 402 |
| Pros and Cons of Inspection | p. 404 |
| The Future of Board Test | p. 405 |
| References | p. 406 |
| Index | p. 407 |
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