Preface xv
Acknowledgments xix
1 Fundamental Concepts and Background 1
Introduction 1
1.1 Communication Systems 1
1.2 History and Overview of Wireless Communication Systems 3
1.3 History and Overview of Wired Communication Systems 4
1.4 Communication System Fundamentals 5
1.4.1 Channel Capacity 5
1.4.2 Bandwidth and Power Tradeoff 6
1.4.3 SNR as a Metric 7
1.4.4 Operating Frequency 8
1.4.5 The Cellular Concept 9
1.4.6 Digital Communications 10
1.4.7 Power Constraint 11
1.4.8 Symbol Constellation 12
1.4.9 Quadrature Basis and Sideband Combination 12
1.4.10 Negative Frequency 13
1.5 Electromagnetics 14
1.5.1 Maxwell’s Equations 14
1.5.2 Application to Circuit Design 14
1.5.3 Signal Propagation in Wireless Medium 15
1.6 Analysis of Circuits and Systems 16
1.6.1 Laplace Transformation 16
1.6.2 Fourier Series 16
1.6.3 Fourier Transform 18
1.6.4 Time and Frequency Domain Duality 18
1.6.5 Z Transform 20
1.6.6 Circuit Dynamics 21
1.6.7 Frequency Domain and Time Domain Simulators 21
1.6.8 Matrix Representation of Circuits 21
1.7 Broadband, Wideband, and Narrowband Systems 26
1.7.1 LC Tank as a Narrowband Element 26
1.7.2 LC Tank at Resonance 27
1.7.3 Q Factor, Power, and Area Metrics 28
1.7.4 Silicon-Specific Considerations 28
1.7.5 Time Domain Behavior 29
1.7.6 Series/Parallel Resonance 29
1.8 Semiconductor Technology and Devices 30
1.8.1 Silicon-Based Processes 31
1.8.2 Unity Current and Power Gain 31
1.8.3 Noise 33
1.8.4 Bipolar vs. MOS 34
1.8.5 Device Characteristics 35
1.8.6 Passive Components 41
1.8.7 Evaluation Testbenches 51
1.9 Key Circuit Topologies 55
1.9.1 Differential Circuits 55
1.9.2 Translinear Circuits 58
1.9.3 Feedback Circuits 59
1.9.4 Cascode Circuits 61
1.9.5 Common Source, Common Gate, and Common Drain Stages 62
1.9.6 Folded Cascode Topology 64
1.10 Gain/Linearity/Noise 65
1.10.1 Noise and Intermodulation Tradeoff 65
1.10.2 Narrowband and Wideband Systems 66
Conclusion 66
References 66
2 Wireless Communication System Architectures 69
Introduction 69
2.1 Fundamental Considerations 70
2.1.1 Center Frequency, Modulation, and Process Technology 70
2.1.2 Frequency Planning 71
2.1.3 Blockers 72
2.1.4 Spurs and Desensing 74
2.1.5 Transmitter Leakage 74
2.1.6 LO leakage and Interference 74
2.1.7 Image 76
2.1.8 Half-IF Interference 76
2.2 Link Budget Analysis 77
2.2.1 Linearity 77
2.2.2 Noise 80
2.2.3 Signal-to-Noise Ratio 82
2.2.4 Receiver Gain 82
2.3 Propagation Effects 83
2.3.1 Path Loss 83
2.3.2 Multipath and Fading 85
2.3.3 Equalization 86
2.3.4 Diversity 86
2.3.5 Coding 87
2.4 Interface Planning 87
2.5 Superheterodyne Architecture 87
2.5.1 Frequency Domain Representation 88
2.5.2 Phase Shift and Image Rejection 89
2.5.3 Transmitter and Receiver 90
2.5.4 Imbalance and Harmonics 90
2.6 Low IF Architecture 91
2.7 Direct Conversion Architecture 92
2.7.1 Advantages 93
2.7.2 Modulation 93
2.7.3 Architecture and Frequency Planning 93
2.7.4 Challenges in the Direct Conversion Receiver 94
2.8 Two-Stage Direct Conversion 102
2.9 Current-Mode Architecture 103
2.10 Subsampling Architecture 104
2.11 Multiband Direct Conversion Radio 105
2.12 Polar Modulator 106
2.13 Harmonic Reject Architecture 108
2.14 Practical Considerations for Transceiver Integration 109
2.14.1 Transmitter Considerations 109
2.14.2 Receiver Considerations 110
Conclusion 111
References 111
3 System Architecture for High-Speed Wired Communications 113
Introduction 113
3.1 Bandlimited Channel 118
3.1.1 Fiber Optical Link 118
3.1.2 Dispersion in Fibers 120
3.1.3 Backplane Multi-Gb/s Data Interface 123
3.1.4 Backplane Channel Loss 124
3.2 Equalizer System Study 129
3.2.1 Equalization Overview 129
3.2.2 Historical Background 131
3.2.3 Equalizer Topology Study 133
3.2.4 Equalizer System Simulation 139
Conclusion 143
References 143
4 Mixed Building Blocks of Signal Communication Systems 144
Introduction 144
4.1 Inverters 145
4.1.1 Key Design Parameters 145
4.1.2 Key Electrical Equations 146
4.1.3 Current Reuse Amplifier 147
4.1.4 Cascade and Fan-Out 148
4.2 Static D Flip-Flop 148
4.3 Bias Circuits 151
4.3.1 Current Sources and Sinks 151
4.3.2 Voltage References 153
4.4 Transconductor Cores 154
4.5 Load Networks 157
4.5.1 Passive Load 157
4.5.2 Active Load 158
4.6 AVersatile Analog Signal Processing Core 159
4.7 Low Noise Amplifier 162
4.7.1 Single-Ended Interfaces 163
4.7.2 Design Steps 163
4.7.3 Gain Expansion 165
4.7.4 Layout Considerations 165
4.7.5 Inductorless LNAs 166
4.7.6 Gain Variation 166
4.8 Power Amplifiers 168
4.8.1 Performance Metrics 168
4.8.2 Classes of Amplifiers 170
4.8.3 Practical Considerations 172
4.8.4 PA Architectures 172
4.8.5 Feedback and Feedforward 174
4.8.6 Predistortion Techniques 177
4.9 Balun 178
4.10 Signal Generation Path 179
4.10.1 Oscillator Circuits 179
4.10.2 Quadrature Generation Networks 188
4.10.3 Passive Hybrid Networks 194
4.10.4 Regenerative Frequency Dividers 194
4.10.5 Phase Locked Loop 195
4.11 Mixers 201
4.11.1 Basic Functionality 201
4.11.2 Architectures 202
4.11.3 Conversion Gain/Loss 203
4.11.4 Noise 204
4.11.5 Port Isolation 205
4.11.6 Receive and Transmit Mixers 205
4.11.7 Impedances 206
4.12 Baseband Filters 207
4.12.1 Classification of Integrated Filters 207
4.12.2 Biquadratic Stages 208
4.12.3 Switched Capacitor Filters 209
4.12.4 Gm-C Filters 211
4.12.5 OP-Amp-RC Filters 213
4.12.6 Calibration of On-Chip Filters 224
4.12.7 Passive Filter Configuration 226
4.13 Signal Strength Indicator (SSI) 226
4.14 ADC/DAC 227
4.15 Latch 230
Conclusion 231
References 231
5 Examples of Integrated Communication Microsystems 235
Introduction 235
5.1 Direct Conversion Receiver Front End 235
5.1.1 Circuit Design 236
5.1.2 The Integration: Interfaces and Layout 242
5.1.3 Compensation and Corrections 243
5.2 Debugging: A Practical Scenario 244
5.3 High-Speed Wired Communication Example 245
5.3.1. Bandlimited Channel 245
5.3.2 Design Example 247
Conclusion 258
References 258
6 Low-Voltage, Low-Power, and Low-Area Designs 260
Introduction 260
6.1. Power Consumption Considerations 261
6.1.1 Active Inductors 261
6.1.2 Adding Transfer Function Zero 263
6.1.3 Driving Point Impedance 263
6.1.4 Stacking Functional Blocks 265
6.2 Device Technology and Scaling 266
6.2.1 Digital and Analog Circuits 266
6.2.2 Supply Voltage, Speed, and Breakdown 266
6.2.3 Circuit Impacts of Increased fT 267
6.2.4 MOSFETs in Weak Inversion 267
6.2.5 Millimeter-Wave Applications 268
6.2.6 Practical Considerations 268
6.3 Low-Voltage Design Techniques 269
6.3.1 Separate DC Paths per Circuit Functionality 269
6.3.2 Transformer Coupled Feedback 270
6.3.3 Positive Feedback 271
6.3.4 Current-Mode Interface 272
6.3.5 Circuits Based on Weak Inversion 273
6.3.6 Voltage Boosting 273
6.3.7 Bulk-Driven Circuits 274
6.3.8 Flipped Voltage Follower 276
6.4 Injection-Locked Techniques 277
6.5. Subharmonic Architectures 279
6.5.1 Formalism 279
6.5.2 System Considerations 280
6.5.3 Antiparallel Diode Pair 281
6.5.4 Active Subharmonic Mixers 284
6.5.5 Subharmonic Architecture Building Blocks 286
6.6. Super-Regenerative Architectures 286
6.6.1 Formalism 287
6.6.2 Architecture and Circuit Illustration 289
6.7. Hearing Aid Applications 290
6.7.1 Architecture Based on Digital/Mixed-Signal Circuits 290
6.7.2 Architecture Based on Subthreshold Current-Mode Circuits 292
6.8. Radio Frequency Identification Tags 297
6.8.1 System Considerations 297
6.8.2 System Architecture 297
6.8.3 Rectifier, Limiter, and Regulator 298
6.8.4 Antenna Design 301
6.9. Ultra-Low-Power Radios 302
Conclusion 303
References 304
7 Packaging for Integrated Communication Microsystems 309
Introduction 309
7.1. Background 311
7.1.1 Trends from 1970 to 1995 311
7.1.2 Trends from 1995 to Today 313
7.1.3 Before 2006 314
7.1.4 After 2006 314
7.2 Elements of a Package 315
7.2.1 Power/GND Planes 315
7.2.2 Package Materials 317
7.3 Current Chip Packaging Technologies 317
7.3.1 Ball Grid Arrays (BGAs) 317
7.3.2 Flip-Chip Technology (FCT) 319
7.3.3 Flip-Chip vs. Wire Bond 319
7.3.4 Choice of Transmission Line 320
7.3.5 Thermal Issues 320
7.3.6 Chip Scale Packaging (CSP) 321
7.4 Driving Forces for RF Packaging Technology 322
7.5 MCM Definitions and Classifications 323
7.6 RF–SOP Modules 325
7.7 Package Modeling and Optimization 329
7.8 Future Packaging Trends 333
7.9 Chip-Package Codesign 334
7.10 Package Models and Transmission Lines 335
7.10.1 Frequency of Operations 335
7.10.2 Bends and Discontinuities 336
7.10.3 Differential Signaling 337
7.11 Calculations for Package Elements 339
7.11.1 Inductance 339
7.11.2 Capacitance 340
7.11.3 Image Theory 341
7.12 Crosstalk 342
7.13 Grounding 343
7.14 Practical Issues in Packaging 344
7.15 Chip-Package Codesign Examples 346
7.16 Wafer Scale Package 349
7.17 Filters Using Bondwire 349
7.18 Packaging Limitation 350
Conclusion 351
References 351
8 Advanced SOP Components and Signal Processing 355
Introduction 355
8.1 History of Compact Design 358
8.2 Previous Techniques in Performance Enhancement 361
8.3 Design Complexities 363
8.4 Modeling Complexities 363
8.5 Compact Stacked Patch Antennas Using LTCC Multilayer Technology 365
8.6 Suppression of Surface Waves and Radiation Pattern Improvement Using SHS Technology 378
8.7 Radiation-Pattern Improvement Using a Compact Soft-Surface Structure 382
8.8 A Package-Level-Integrated Antenna Based on LTCC Technology 395
Conclusion 401
References 401
9 Simulation and Characterization of Integrated Microsystems 404
Introduction 404
9.1 Computer-Aided Analysis of Wireless Systems 404
9.1.1 Operating Point Analysis 405
9.1.2 Impedance Matching 407
9.1.3 Tuning at Resonance 407
9.1.4 Transient Analysis 408
9.1.5 Noise Analysis 409
9.1.6 Linearity Analysis 410
9.1.7 Parasitic Elements 413
9.1.8 Process Variation 413
9.2 Measurement Equipments and their Operation 413
9.2.1 DC/Operating Point 413
9.2.2 C–V Measurement 414
9.2.3 Vector Network Analyzer and S-Parameter Measurements 415
9.2.4 Spectrum Analyzer (SA) 416
9.3 Network Analyzer Calibration 418
9.3.1 Overview of Network Analyzer Calibration 418
9.3.2 Types of Calibration 420
9.3.3 SOLT Calibration 420
9.3.4. TRL Calibration 424
9.4 Wafer Probing Measurement 429
9.4.1 Calibration Quantification of Random Errors 429
9.4.2 On-Wafer Measurement at the W-Band (75–110 GHz) 430
9.4.3 On-Wafer Microstrip Characterization Techniques 435
9.4.4 On-Wafer Package Characterization Technique 440
9.5 Characterization of Integrated Radios 448
9.6 In the Lab 451
9.6.1 Operating Point 451
9.6.2 Functionality Test 451
9.6.3 Impedance Matching 451
9.6.4 Conversion Gain 453
9.6.5 Linearity 453
9.6.6 Nonlinear Noise Figure 454
9.6.7 I/Q Imbalance 455
9.6.8 DC Offset 456
Conclusion 457
References 458
Appendix A Compendium of the TRL Calibration Algorithm 459
Appendix A 462
Index 469
