VLSI Memory Chip Design

By: Kiyoo Itoh

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Hardcover | 13 March 2001

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508 Pages

Dimensions(cm)
23.5 x 15.88 x 1.91

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This book features a systematic description of microelectronic device design ranging from the basics to current topics, such as low-power/ultralow-voltage designs including subthreshold current reduction, memory subsystem designs for modern DRAMs and various on-chip supply-voltage conversion techniques. It also covers process and device issues as well as design issues relating to systems, circuits, devices and processes, such as signal-to-noise and redundancy.

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An Introduction to Memory Chip Design	p. 1
Introduction	p. 1
The Internal Organization of Memory Chips	p. 3
The Memory Cell Array	p. 3
The Peripheral Circuit	p. 5
The I/O Interface Circuit	p. 6
Categories of Memory Chip	p. 6
General Trends in DRAM Design and Technology	p. 11
The History of Memory-Cell Development	p. 11
The Basic Operation of The 1-T Cell	p. 15
Advances in DRAM Design and Technology	p. 19
General Trends in SRAM Design and Technology	p. 24
The History of Memory-Cell Development	p. 24
The Basic Operation of a SRAM Cell	p. 26
Advances in SRAM Design and Technology	p. 29
General Trends in Non-Volatile Memory Design and Technology	p. 31
The History of Memory-Cell Development	p. 31
The Basic Operation of Flash Memory Cells	p. 34
Advances in Flash-Memory Design and Technology	p. 46
The Basics of RAM Design and Technology	p. 49
Introduction	p. 49
Devices	p. 49
MOSFETs	p. 49
Capacitors	p. 57
Resistors	p. 60
Wiring and Wiring Materials	p. 61
Silicon Substrates and CMOS Latch-Up	p. 65
Other Devices	p. 67
NMOS Static Circuits	p. 67
The dc Characteristics of an Inverter	p. 68
The ac Characteristics of an Inverter	p. 70
The Improved NMOS Static Inverter	p. 74
NMOS Dynamic Circuits	p. 76
The Dynamic Inverter	p. 76
The Bootstrap Driver	p. 77
CMOS Circuits	p. 79
The dc Characteristics	p. 80
The ac Characteristics	p. 82
Basic Memory Circuits	p. 83
The Inverter and the Basic Logic Gate	p. 83
The Current Mirror	p. 83
The Differential Amplifier	p. 83
The Voltage Booster	p. 87
The Level Shifter	p. 88
The Ring Oscillator	p. 88
The Counter	p. 89
The Scaling Law	p. 90
Constant Electric-Field Scaling	p. 90
Constant Operation-Voltage Scaling	p. 92
Combined Scaling	p. 92
Lithography	p. 93
Packaging	p. 94
DRAM Circuits	p. 97
Introduction	p. 97
High-Density Technology	p. 98
High-Performance Circuits	p. 100
The catalog Specifications of the Standard DRAM	p. 102
Operational Conditions	p. 102
Modes of Operation and Timing Specifications	p. 105
The Basic Configuration and Operation of the DRAM Chip	p. 110
Chip Configuration	p. 110
Address Multiplexing	p. 111
Fundamental Chip Technologies	p. 113
A Larger Memory Capacity and Scaled-Down Devices	p. 113
High S/N Ratio Circuits	p. 116
Low Power Circuits	p. 117
High-Speed Circuits	p. 123
The Multidivision of a Memory Array	p. 128
The Multidivided Data Line and Word Line	p. 131
The Multidivided Data Line	p. 132
The Multidivided Word Line	p. 139
Read and Relevant Circuits	p. 141
The Address Buffer	p. 141
The Address Decoder	p. 144
The Word Driver	p. 147
The Sensing Circuit	p. 157
The Common I/O-Line Relevant Circuit	p. 167
The Data-Output Buffer	p. 172
Write and Relevant Circuits	p. 174
Refresh-Relevant Circuits	p. 175
Refresh Schemes	p. 175
The Extension of Data-Retention Time in Active Mode	p. 176
Current Reduction Circuits in Data-Retention Mode	p. 176
Redundancy Techniques	p. 178
Issues for Large-Memory-Capacity Chips	p. 184
Intra-Subarray Replacement Redundancy	p. 185
Inter-Subarray Replacement Redundancy	p. 189
The Repair of dc-Characteristics Faults	p. 191
On-Chip Testing Circuits	p. 192
High Signal-to-Noise Ratio DRAM Design and Technology	p. 195
Introduction	p. 195
Trends in High S/N Ratio Design	p. 195
The Signal Charge	p. 197
Leakage Charge	p. 204
The Soft-Error Critical Charge	p. 208
The Data-Line Noise Charge	p. 210
Data-Line Noise Reduction	p. 210
Noise Sources and Their Reduction	p. 210
Word-Line Drive Noise	p. 213
Data-Line and Sense-Amplifier Imbalances	p. 217
Word-Line to Data-Line Coupling Noise	p. 230
Data-Line Interference Noise	p. 237
Power-Supply Voltage Bounce	p. 240
Variation in the Reference Voltage	p. 241
Other Noises	p. 244
Summary	p. 247
On-Chip Voltage Generators	p. 249
Introduction	p. 249
The Substrate-Bias Voltage (V_BB) Generator	p. 251
The Roles of the V_BB generator	p. 251
Basic Operation and Design Issues	p. 256
Power-On Characteristics	p. 258
Characteristics in the High-V_DD Region	p. 264
The V_BB Bump	p. 266
Substrate-Current Generation	p. 269
Triple-Well Structures	p. 272
Low-Power V_BB Generators	p. 273
The Voltage Up-Converter	p. 276
The Roles of the Voltage Up-Converter	p. 276
Design Approaches and Issues	p. 278
High Boost-Ratio Converters	p. 283
Low-Power, High Supply Current Converters	p. 285
The Voltage Down-Converter	p. 290
The Roles of the Voltage Down-Converter	p. 290
The Negative-Feedback Converter and Design Issues	p. 293
Optimum Design	p. 297
Phase Compensation	p. 301
Reference-Voltage Generators	p. 316
Burn-In Test Circuits	p. 323
Voltage Trimming	p. 327
Low-Power Circuits	p. 329
The Half-V_DD Generator	p. 332
Examples of Advanced On-Chip Voltage Generators	p. 333
High-Performance Subsystem Memories	p. 339
Introduction	p. 339
Hierarchical Memory Systems	p. 341
Memory Hierarchy	p. 341
Improvements in Memory-Subsystem Performance	p. 344
Memory-Chip Performance	p. 349
Memory-Subsystem Technologies	p. 354
Wide-Bit I/O Chip Configurations	p. 354
Parallel Operation of Multidivided Arrays	p. 354
Multibank Interleaving	p. 357
Synchronous Operation	p. 358
Pipeline/Prefetch Operations	p. 362
High-Speed Clocking Schemes	p. 363
Terminated I/O Interfaces	p. 363
High-Density Packaging	p. 364
High-Performance Standard DRAMs	p. 365
Trends in Chip Development	p. 365
Synchronous DRAM	p. 368
Rambus DRAM	p. 380
Embedded Memories	p. 383
Low-Power Memory Circuits	p. 389
Introduction	p. 389
Sources and Reduction of Power Dissipation in a RAM Subsystem	p. 392
Wide-Bit I/O Chip Configuration	p. 393
Small Package	p. 394
The Low-Voltage Data-Bus Interface	p. 396
Sources of Power Dissipation in the RAM Chip	p. 402
Active Power Sources	p. 402
Data-Retention Power Sources	p. 405
Low-Power DRAM Circuits	p. 406
Active Power Reduction	p. 406
Data-Retention Power Reduction	p. 412
Low-Power SRAM Circuits	p. 413
Active Power Reduction	p. 413
Data-Retention Power Reduction	p. 423
Ultra-Low-Voltage Memory Circuits	p. 425
Introduction	p. 425
Design Issues for Ultra-Low-Voltage RAM Circuits	p. 426
Reduction of the Subthreshold Current	p. 426
Stable Memory-Cell Operation	p. 432
Suppression of, or Compensation for, Design Parameter Variations	p. 433
Power-Supply Standardization	p. 435
Ultra-Low-Voltage DRAM Circuits	p. 437
Gate Boosting Circuit	p. 439
The Multi-V_T Circuit	p. 440
The Gate-Source Back-Biasing Circuit	p. 442
The Well Control Circuit	p. 456
The Source Control Circuit	p. 461
The Well and Source Control Circuit	p. 462
Ultra-Low-Voltage SRAM Circuits	p. 463
Ultra-Low-Voltage SOI Circuits	p. 466
References	p. 473
Index	p. 489
Table of Contents provided by Publisher. All Rights Reserved.

VLSI Memory Chip Design

At a Glance

Hardcover

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How to return your order

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