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Verification Plans : The Five-Day Verification Strategy for Modern Hardware Verification Languages - Peet James

Verification Plans

The Five-Day Verification Strategy for Modern Hardware Verification Languages

By: Peet James

Hardcover | 31 October 2003

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The task of verification is always larger than the task of the design effort. Why? Because the verification system has to encompass the entire functionality of the device under verification. It has to mimic the real world environment that the device will actual operate in. It needs to catch functional errors. It needs to give feedback information to guide further verification. The design effort proceeds from a design specification. Verification systems need to proceed from a verification plan. A comprehensive document that describes the verification system and all its components. A plan that details how the verification system will be built. With the advent of hardware verification languages, today's verifications systems have grown in complexity making verification plans even more paramount. This work is a practical guide on how to get a verification team jumpstarted into verification success by the joint creation of a verification plan. The book includes: a detailed five day approach that gives day-by-day, step-by-step instructions on how to design and document your verification system; an introduction to hardware verification languages, their pseudo-random mindset, their enabling methodologies (generation, checking and coverage), and how these effect the development of a verification plan; practical guidance in common people issues, formatting decisions and information extraction methods to enhance your verification plan brainstorming sessions; and an appendix full of verification plan examples and support documents.
Industry Reviews
"In this book, Peet gives every engineer trying to do functional verification a jump-start on getting it under control...His technique...is soundly grounded in the real world, honed through years of experience and practice. If you adopt this approach, it will improve the speed with which verification plans are produced, improve their quality, help eliminate redundant work, and reduce unnecessary work...But wait, there's more. Peet not only tells you how to do it, he tells you why you should do it a certain way, and why Hardware Verification Languages give you an advantage (motivation for you to check out the new techniques and ammunition for your presentations to management)...I have been helped already by what Peet gives in his book. I'm keeping my copy right next to Janick's book."
(Glenn Hunt, Texas Instruments)

You Can Find This Book In

Non-FictionEngineering & TechnologyElectronics & Communications EngineeringElectronics EngineeringCircuits & ComponentsComputing & I.T.Computer HardwareMaintenance & RepairsComputer ScienceSystems Analysis & DesignComputer Architecture & Logic DesignComputer Programming & Software Development
Programming & Scripting LanguagesGraphical & Digital Media ApplicationsComputer-Aided Design CAD

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Published: 5th November 2012

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