Transactions on High-Performance Embedded Architectures and Compilers I

By: Per StenstrÃ¶m, Mike O'Boyle (Editor), Francois Bodin (Editor)

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Paperback | 13 April 2007

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Transactions on HiPEAC is a new journal which aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. It publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. Its scope covers all aspects of computer architecture, code generation and compiler optimization methods.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Computing & I.T.Computer Science Computer Architecture & Logic Design Computer Programming & Software Development Compilers & Interpreters Programming & Scripting Languages Computer Networking & Communications EDI Electronic Data Interchange

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Transactions on HiPEAC I
High performance processor chips	p. 1
High-performance embedded architecture and compilation roadmap	p. 5
First international conference on high-performance embedded architectures and compilers, HiPEAC 2005 : best papers
Quick and practical run-time evaluation of multiple program optimizations	p. 34
Specializing cache structures for high performance and energy conservation in embedded systems	p. 54
GCH : hints for triggering garbage collections	p. 74
Memory-centric security architecture	p. 95
Power aware external bus arbitration for system-on-a-chip embedded systems	p. 116
Optimizing compilers
Convergent compilation applied to loop unrolling	p. 140
Finding and applying loop transformations for generating optimized FPGA implementations	p. 159
Dynamic and on-line design space exploration for reconfigurable architectures	p. 179
Automatic discovery of coarse-grained parallelism in media applications	p. 194
An approach for enhancing inter-processor data locality on chip multiprocessors	p. 214
ACM international conference on computing frontiers 2006 : best papers
Hardware/software architecture for real-time ECG monitoring and analysis leveraging MPSoC technology	p. 239
Using application bisection bandwidth to guide tile size selection for the synchroscalar tile-based architecture	p. 259
Static cache partitioning robustness analysis for embedded on-chip multi-processors	p. 279
Selective code compression scheme for embedded systems	p. 298
A prefetching algorithm for multi-speed disks	p. 317
Reconfiguration strategies for environmentally powered devices : theoretical analysis and experimental validation	p. 341
Table of Contents provided by Blackwell. All Rights Reserved.

Transactions on High-Performance Embedded Architectures and Compilers I

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