The Student's Guide to VHDL

By: Peter Ashenden

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Paperback | 19 May 2008 | Edition Number 2

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528 Pages

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Annotated

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22.86 x 19.68 x 2.54

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The Student's Guide to VHDL is a condensed edition of The Designer's Guide to VHDL, the most widely used textbook on VHDL for digital system modeling. The Student's Guide is targeted as a supplemental reference book for computer organization and digital design courses.

Since publication of the first edition of The Student's Guide, the IEEE VHDL and related standards have been revised. The Designer's Guide has been revised to reflect the changes, so it is appropriate that The Student's Guide also be revised.
In The Student's Guide to VHDL, 2nd Edition, we have included a design case study illustrating an FPGA-based design flow. The aim is to show how VHDL modeling fits into a design flow, starting from high-level design and proceeding through detailed design and verification, synthesis, FPGA place and route, and final timing verification. Inclusion of the case study helps to better serve the educational market. Currently, most college courses do not formally address the details of design flow. Students may be given informal guidance on how to proceed with lab projects. In many cases, it is left to students to work it out for themselves. The case study in The Student's Guide provides a reference design flow that can be adapted to a variety of lab projects.

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Non-Fiction Computing & I.T.Computer Science Systems Analysis & Design Computer Architecture & Logic Design Engineering & Technology Technology in General Operating Systems Computer Hardware

Preface	p. xiii
Fundamental Concepts	p. 1
Modeling Digital Systems	p. 1
Domains and Levels of Modeling	p. 3
Modeling Example	p. 3
Modeling Languages	p. 7
VHDL Modeling Concepts	p. 7
Elements of Behavior	p. 8
Elements of Structure	p. 10
Mixed Structural and Behavioral Models	p. 12
Test Benches	p. 13
Analysis, Elaboration and Execution	p. 14
Learning a New Language: Lexical Elements and Syntax	p. 16
Lexical Elements	p. 17
Comments	p. 17
Identifiers	p. 19
Reserved Words	p. 20
Special Symbols	p. 22
Numbers	p. 22
Characters	p. 23
Strings	p. 23
Bit Strings	p. 24
Syntax Descriptions	p. 26
Exercises	p. 29
Scalar Data Types and Operations	p. 31
Constants and Variables	p. 31
Constant and Variable Declarations	p. 31
Variable Assignment	p. 33
Scalar Types	p. 34
Type Declarations	p. 34
Integer Types	p. 35
Floating-Point Types	p. 38
Physical Types	p. 39
Time	p. 42
Enumeration Types	p. 43
Characters	p. 44
Booleans	p. 46
Bits	p. 47
Standard Logic	p. 48
Condition Conversion	p. 49
Type Classification	p. 50
Subtypes	p. 51
Type Qualification	p. 53
Type Conversion	p. 53
Attributes of Scalar Types	p. 54
Expressions and Predefined Operations	p. 57
Exercises	p. 61
Sequential Statements	p. 65
If Statements	p. 65
Case Statements	p. 68
Null Statements	p. 74
Loop Statements	p. 75
Exit Statements	p. 76
Next Statements	p. 79
While Loops	p. 80
For Loops	p. 82
Summary of Loop Statements	p. 85
Assertion and Report Statements	p. 85
Exercises	p. 92
Composite Data Types and Operations	p. 95
Arrays	p. 95
Multidimensional Arrays	p. 98
Array Aggregates	p. 99
Array Attributes	p. 103
Unconstrained Array Types	p. 105
Predefined Array Types	p. 106
Strings	p. 106
Boolean Vectors, Integer Vectors, Real Vectors, and Time Vectors	p. 106
Bit Vectors	p. 107
Standard-Logic Arrays	p. 107
String and Bit-String Literals	p. 108
Unconstrained Array Element Types	p. 109
Unconstrained Array Ports	p. 111
Array Operations and Referencing	p. 114
Logical Operators	p. 114
Shift Operators	p. 116
Relational Operators	p. 117
Maximum and Minimum Operations	p. 118
The Concatenation Operator	p. 119
To_String Operations	p. 119
Array Slices	p. 120
Array Type Conversions	p. 121
Arrays in Case Statements	p. 124
Matching Case Statements	p. 125
Records	p. 127
Record Aggregates	p. 130
Unconstrained Record Element Types	p. 130
Exercises	p. 133
Basic Modeling Constructs	p. 135
Entity Declarations and Architecture Bodies	p. 135
Concurrent Statements	p. 139
Signal Declarations	p. 139
Behavioral Descriptions	p. 141
Signal Assignment	p. 141
Conditional Signal Assignments	p. 144
Selected Signal Assignments	p. 145
Signal Attributes	p. 147
Wait Statements	p. 149
Delta Delays	p. 153
Transport and Inertial Delay Mechanisms	p. 156
Process Statements	p. 162
Concurrent Signal Assignment Statements	p. 164
Concurrent Simple Signal Assignments	p. 164
Concurrent Conditional Signal Assignment	p. 165
Concurrent Selected Signal Assignments	p. 169
Concurrent Assertion Statements	p. 171
Entities and Passive Processes	p. 172
Structural Descriptions	p. 174
Design Processing	p. 184
Analysis	p. 184
Design Libraries and Contexts	p. 186
Elaboration	p. 188
Execution	p. 191
Exercises	p. 192
Subprograms	p. 201
Procedures	p. 201
Return Statement in a Procedure	p. 206
Procedure Parameters	p. 207
Signal Parameters	p. 211
Default Values	p. 214
Unconstrained Array Parameters	p. 215
Summary of Procedure Parameters	p. 218
Concurrent Procedure Call Statements	p. 219
Functions	p. 221
Functional Modeling	p. 224
Pure and Impure Functions	p. 224
The Function now	p. 226
Overloading	p. 227
Overloading Operator Symbols	p. 228
Visibility of Declarations	p. 230
Exercises	p. 234
Packages and Use Clauses	p. 239
Package Declarations	p. 239
Subprograms in Package Declarations	p. 244
Constants in Package Declarations	p. 244
Package Bodies	p. 246
Local Packages	p. 249
Use Clauses	p. 251
Visibility of Used Declarations	p. 255
Exercises	p. 258
Resolved Signals	p. 261
Basic Resolved Signals	p. 261
Composite Resolved Subtypes	p. 266
Summary of Resolved Subtypes	p. 271
IEEE std_logic_1164 Resolved Subtypes	p. 272
Resolved Signals, Ports, and Parameters	p. 274
Resolved Ports	p. 276
Driving Value Attribute	p. 279
Resolved Signal Parameters	p. 280
Exercises	p. 281
Predefined and Standard Packages	p. 287
The Predefined Packages standard and env	p. 287
IEEE Standard Packages	p. 290
Standard VHDL Mathematical Packages	p. 290
Real Number Mathematical Package	p. 290
Complex Number Mathematical Package	p. 293
The std_logic_1164 Multivalue Logic System	p. 295
Standard Integer Numeric Packages	p. 298
Package Summary	p. 307
Operator Overloading Summary	p. 307
Conversion Function Summary	p. 309
Strength Reduction Function Summary	p. 311
Exercises	p. 312
Aliases	p. 315
Aliases for Data Objects	p. 315
Aliases for Non-Data Items	p. 320
Exercises	p. 323
Generic Constants	p. 325
Generic Constants	p. 325
Exercises	p. 332
Components and Configurations	p. 335
Components	p. 335
Component Declarations	p. 335
Component Instantiation	p. 337
Packaging Components	p. 338
Configuring Component Instances	p. 340
Basic Configuration Declarations	p. 340
Configuring Multiple Levels of Hierarchy	p. 343
Direct Instantiation of Configured Entities	p. 346
Generic and Port Maps in Configurations	p. 347
Deferred Component Binding	p. 353
Exercises	p. 355
Generate Statements	p. 359
Generating Iterative Structures	p. 359
Conditionally Generating Structures	p. 365
Exercises	p. 372
Design for Synthesis	p. 375
Synthesizable Subsets	p. 375
Use of Data Types	p. 376
Scalar Types	p. 377
Composite and Other Types	p. 378
Interpretation of Standard Logic Values	p. 379
Modeling Combinational Logic	p. 380
Modeling Sequential Logic	p. 383
Modeling Edge-Triggered Logic	p. 384
Level-Sensitive Logic and Inferring Storage	p. 392
Modeling State Machines	p. 394
Modeling Memories	p. 396
Synthesis Attributes	p. 400
Metacomments	p. 410
Exercises	p. 411
Case Study: System Design Using the Gumnut Core	p. 413
Overview of the Gumnut	p. 413
Instruction Set Architecture	p. 413
External Interface	p. 418
The Gumnut Entity Declaration	p. 420
Instruction and Data Memories	p. 421
A Digital Alarm Clock	p. 425
System Design	p. 425
Synthesizing and Implementing the Alarm Clock	p. 433
Exercises	p. 435
Standard Packages	p. 437
The Predefined Package standard	p. 437
The Predefined Package env	p. 441
The Predefined Package textio	p. 441
Standard VHDL Mathematical Packages	p. 443
The math_real Package	p. 443
The math_complex Package	p. 445
The std_logic_1164 Multivalue Logic System Package	p. 446
Standard Integer Numeric Packages	p. 450
The numeric_bit Package	p. 450
The numeric_std Package	p. 456
The numeric_bit_unsigned Package	p. 457
The numeric_std_unsigned Package	p. 459
VHDL Syntax	p. 461
Design File	p. 463
Library Unit Declarations	p. 463
Declarations and Specifications	p. 465
Type Definitions	p. 468
Concurrent Statements	p. 470
Sequential Statements	p. 472
Interfaces and Associations	p. 475
Expressions and Names	p. 476
Answers to Exercises	p. 479
References	p. 497
Index	p. 499
Table of Contents provided by Ingram. All Rights Reserved.

The Student's Guide to VHDL

At a Glance

Paperback

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