The Design of a Microprocessor

1. Introduction.- 1. Introduction.- 1.1. Overview.- 1.2. Structure of the Book.- 1.3. S/370 Architecture.- 1.4. Layered Processor Structure.- 2. Logic Design.- 2.1. Design Overview.- 2.1.1 Introduction.- 2.1.1.1 Design Goals.- 2.1.1.2 Processor Structure.- 2.1.2 Chip Set Description.- 2.1.2.1 Processing Unit (CPU) Chip.- 2.1.2.2 Memory Management Unit (MMU) Chip.- 2.1.2.3 Storage Controller (STC) Chip.- 2.1.2.4 Clock Chip.- 2.1.2.5 Control Store (CS) Chip.- 2.1.2.6 Floating Point Unit (FPU) Chip.- 2.1.3 Chip Interconnection Busses.- 2.1.4 Cache Timing Considerations.- 2.1.5 Miscellaneous.- 2.1.5.1 Reliability, Availability, Serviceability (RAS).- 2.1.5.2 System Measurement Interface (SMI).- 2.1.5.3 Other Processor Components.- 2.2. Processing Unit Chip.- 2.2.1 Design Considerations.- 2.2.2 Block Diagram Description.- 2.2.3 Modes of Operation.- 2.2.3.1 S/370 Mode.- 2.2.3.2 Micromode.- 2.2.3.3 Forced Operations.- 2.2.4 Pipelining.- 2.2.5 Data Local Store Layout.- 2.2.6 Micro Instructions.- 2.2.6.1 Data Local Store Addressing.- 2.2.6.2 Microinstructions Types and Formats.- 2.2.6.3 Reducing the Number of Branch Microinstructions.- 2.2.7 Data Flow Logic.- 2.2.7.1 ALU, Shift, Units and DLS.- 2.2.7.2 Bus Unit and Processor Bus Operations.- 2.2.8 Prefetch Buffer.- 2.2.9 Floating-Point Coprocessor Interface.- 2.3 Timer Support.- 2.3.1 Introduction to the Timer Functions.- 2.3.2 Format of the Timer Binary Counters.- 2.3.3 Functional Description and Block Diagram.- 2.3.4 Communication with the CPU.- 2.3.5 Programmable Clock Cycle Time.- 2.4. Memory Management Unit Chip.- 2.4.1 Overview.- 2.4.2 Storage Hierarchy Elements.- 2.4.2.1 Virtual Storage Addressing.- 2.4.2.2 Translation-Lookaside Buffer.- 2.4.2.3 Cache Operation.- 2.4.2.4 Key Store.- 2.4.2.5 Combined Operation.- 2.4.3 MMU Chip Data Flow.- 2.4.4 Array Macros.- 2.4.4.1 Translation-Lookaside Buffer (TLB).- 2.4.4.2 Cache Directory.- 2.4.4.3 Cache Array.- 2.4.4.4 Keystore.- 2.4.5 Storage Controller Interface.- 2.5. Storage Controller Chip.- 2.5.1 STC Chip Structure.- 2.5.1.1 Memory Control Unit.- 2.5.1.2 Error Correction Unit.- 2.5.1.3 STC Chip Interfaces.- 2.5.2 Memory Organization and Control.- 2.5.2.1 Overview.- 2.52.2 Memory Card.- 2.5.2.3 Memory Performance.- 2.5.2.4 Fetch Operation.- 2.5.2.5 Store Operation.- 2.5.3 Data Integrity.- 2.5.3.1 Refresh.- 2.5.3.2 ECC (Error Correction Codes).- 2.5.3.3 Complement Retry.- 2.5.3.4 Redundant Bit.- 2.5.3.5 Scrub.- 2.5.3.6 Address Fault Protection.- 2.5.4 Diagnostics.- 2.5.5 Personalization.- 2.6. Floating Point Coprocessor.- 2.6.1 General Description.- 2.6.2 Floating-Point Instructions and Data Format.- 2.6.3 FPU Interface and Communication.- 2.6.4 Chip Logical Description.- 2.6.4.1 Overview.- 2.6.4.2 Exponent Dataflow.- 2.6.4.3 Mantissa Dataflow.- 2.6.5 Reliability, Checking and Testing.- 2.6.5.1 Reliability.- 2.6.5.2 Checking.- 2.6.6 Performance.- 2.7. Bus Interface Chips.- 2.7.1 Overview.- 2.7.2 MBA Chip.- 2.7.3 BCU Chip.- 2.8. Clock Chip.- 2.8.1 Central Clock Generation Versus Distributed Clock Generation.- 2.8.2 Logical Implementation.- 2.8.3 Timing Tolerances, Reset and Checking.- 2.9. Clocking.- 2.9.1 Clock Signal Types.- 2.9.2 Clock Generation Flow.- 2.9.3 Clock Pulse Generation.- 2.9.4 Evaluation of the Clock Skews.- 2.9.5 Logic Chip Clock Distribution.- 2.9.5.1 Standard On-Chip Clock Distribution.- 2.9.5.2 High Performance On-Chip Clock Distribution.- 2.9.6 Evaluation of the Clocking Scheme.- 2.9.7 Clock Variation.- 2.10. Processor Bus.- 2.10.1 Processor Bus Connections.- 2.10.2 Processor Bus Implementation.- 2.10.3 Processor Bus Operation Example.- 2.11. Reliability, Availability, Serviceability.- 2.11.1 Overview.- 2.11.2 RAS Strategy and Requirements.- 2.11.3 Initial Chip Set Start and Loading.- 2.11.4 Error Detection.- 2.11.5 Machine Check Handling.- 2.11.6 Support Interface.- 2.11.6.1 Unit Support Interface Description.- 2.11.6.2 Unit Support Interface Operation.- 3. Logic Design Tools.- 3.1. Logic Design System Overview.- 3.2. Hardware Design Language.- 3.2.1 Overview.- 3.2.2 The Design Level.- 3.2.3 Design Rules Checks.- 3.2.4 The Macro Level.- 3.2.5 The System Level.- 3.2.6 Design System Dataflow.- 3.2.7 Overall Comparison with VHDL.- 3.3. Logic Synthesis.- 3.3.1 Overview.- 3.3.2 Logic Synthesis Methodology.- 3.3.3 LSS Overview.- 3.3.4 Technology Information.- 3.3.5 Partitioned Synthesis.- 3.3.6 Synthesis Experience.- 3.4 Logic Synthesis Design Experience.- 3.4.1 Overview.- 3.4.2 The Design System.- 3.4.3 Challenges in Using LSS.- 3.4.4 Delay Optimization and the Use of LSS.- 3.4.5 Results and Designers' Echo.- 3.4.6 Discussion.- 3.4.7 Conclusions.- 3.5. Timing Analysis and Verification.- 3.5.1 Overview.- 3.5.2 Delay Equations.- 3.5.3 Capacitance Estimate.- 3.5.4 Multiple Clock Designs.- 3.5.5 Multiple Cycle Paths.- 3.5.6 Global Timing Correction for Logic Synthesis.- 3.6. Logic Design Verification.- 3.6.1 Overview.- 3.6.2 The Concept of Using Logic Simulation.- 3.6.3 Modelling Requirements.- 3.6.4 The Phases in Logic Design Verification.- 3.6.5 What Drives the Simulation - Testcases.- 3.6.6 The Testcase Execution Control Program.- 3.7. Logic Simulation.- 3.7.1 Overview.- 3.7.2 Hardware Specification Languages.- 3.7.3 Compilation Techniques.- 3.7.4 Simulation Control.- 3.7.5 Distributed Simulation.- 4. CWp Technology.- 4.1 Chip Technology Overview.- 4.1.1 Technology.- 4.1.2 Circuit Libary and Chip Image.- 4.2. Master Image Chip.- 4.3. VLSI Book Library and Array Macros.- 4.3.1 Cell Design.- 4.3.2 Circuit Library.- 4.3.3 Sub-Circuit Elements.- 4.3.4 Macro Design.- 4.4. A New I/O Driver Circuit.- 4.4.1 Problem Definition.- 4.4.2 Driver Family.- 4.4.3 Dynamic Control.- 4.5. Embedded Array Macros.- 4.5.1 Array Configurations.- 4.5.2 Storage Cell and Circuit Design.- 4.5.3 Array Integration.- 4.5.4 Testing of Embedded Arrays.- 4.6. Packaging.- 4.6.1 Overview.- 4.6.2 First Level Packaging.- 4.6.3 Electrical Considerations.- 4.6.4 Second Level Package.- 5. Semiconductor Technology.- 5.1. Design for Testability.- 5.1.1 Overview.- 5.1.2 Failure Types and Failure Models.- 5.1.3 Structural Test.- 5.1.4 Design for Testability.- 5.1.5 LSSD (Level Sensitive Scan Design).- 5.1.5.1 Overview.- 5.1.5.1 LSSD Rules and Partitioning.- 5.1.6 Additional Test Features.- 5.1.6.1. Internal Tristate Driver.- 5.1.6.2 Observation Points.- 5.1.6.3 Logic Circuit Layout Optimized for Defect Sensitivities.- 5.1.7 Random Pattern Testing.- 5.1.8 Auto Diagnostic.- 5.2. Test and Characterization.- 5.2.1 Wafer and Module Test.- 5.2.1.1 Test Overview.- 5.2.1.2 Process Parameter Test.- 5.2.1.3 Logic Test on Wafer and Module.- 5.2.1.4 Functional Pattern Test.- 5.2.1.5 Logic Test Equipment.- 5.2.2 Failure Localization and Characterization.- 5.2.2.1 Second Metal Test.- 5.2.2.2 Internal Probing Station.- 5.2.2.3 Fail Locating by Internal Probing.- 5.2.2.4 Performance Verification.- 5.3. Semiconductor Process / Device Design.- 5.3.1 The Semiconductor Process.- 5.3.2 Layout Rules.- 5.3.3 Electrical Device Properties.- 5.4. Failure Analysis.- 5.4.1 Purpose of Failure Analysis.- 5.4.2 Failure Analysis Strategy and Methods.- 5.4.3 Failure Analysis Examples.- 5.4.3.1 Particles.- 5.4.3.2 Metal Interruptions at Steep Steps.- 5.4.3.3 Oxide Residues in Contact Holes.- 5.4.3.4 Leakage between Vdd and Ground.- 5.4.3.5 Signal to Ground Leakage.- 5.4.3.6 Source-Drain Leakage.- 5.4.3.7 Latch-Up.- 6. Physical Design Tools.- 6.1 Physical Design Concept.- 6.2 Hierarchical Physical Design.- 6.2.1 Methodology.- 6.2.2 Partitioning and Floorplanning.- 6.2.3 Implantation.- 6.2.4 Detailed Processing.- 6.2.5 Chip Assembly.- 6.3 Hierarchical Layout and Checking.- 6.3.1 Chip Layout.- 6.3.2 Chip Merge and Final Data Generation.- 6.3.3 Checking.- 6.4. Delay Calculator and Timing Analysis.- 6.4.1 Circuit Delay.- 6.4.2 Calculation Method and Simulation.- 6.4.3 Fitting Method (Least Square Fit).- 6.5. Physical Design Experience.- 6.5.1 Master Image Development.- 6.5.2 Physical Design.- 6.5.3 Hardware Bring-Up.- 6.5.4 Lessons Learned.- 7. System Implementation.- 7.1. ES/9370 System Overview.- 7.2. High Level Microprogramming in 1370.- 7.2.1 Overview.- 7.2.2 Concepts and Facilities.- 7.2.2.1 Processor Structure.- 7.2.2.2 Instruction Interpretation.- 7.2.2.3 Control Spaces and Associated Instructions.- 7.2.2.4 Mode Control and Associated Instructions.- 7.2.3 ES/9370 Realization.- 7.2.3.1 ES/9370 System Structure.- 7.2.3.2 Service Processor to I/O Controller Communication.- 7.2.3.3 Extending the Kernel Functions.- 7.2.3.4 Simulation Concept for I370 Programs.- 7.2.4 Conclusions and Outlook.- 7.3. System Bring-Up and Test.- 7.3.1 Overview.- 7.3.2 Bring-Up Strategy.- 7.3.3 Basic Bring-Up Process.- 7.3.3.1 Sub-Architectural Verification.- 7.3.3.2 Architecture Verification.- 7.3.3.3 Testing Under the PAS Control Program.- 7.3.3.4 System I/O and Interaction Testing.- 7.3.4 System Bring-Up.- 7.3.5 Regression Testing.- 7.3.6 Bring-Up Results and Error Corrections.- 7.3.6.1 Basic Bring-Up.- 7.3.6.2 System Bring-Up.- 7.3.7 Summary and Conclusions.- 7.4. Outlook.- Authors.- References.