| About the author | p. xi |
| Acknowledgements | p. xiii |
| Preface | p. xv |
| Introduction | p. 1 |
| Technical challenges in mixed-signal integration | p. 1 |
| The switched-current technique | p. 2 |
| About this book | p. 4 |
| An introduction to the SI technique | p. 4 |
| SI circuit design issues | p. 5 |
| SI circuit implementation examples | p. 5 |
| Appendix | p. 6 |
| References | p. 6 |
| An Introduction to the SI Technique | p. 7 |
| Switched-Current Circuits | p. 9 |
| Current-mode building blocks | p. 9 |
| The current mirror | p. 9 |
| First and second generation SI memory cells | p. 10 |
| OTA based current S/H circuits | p. 12 |
| Comparators | p. 12 |
| D/A-converters | p. 13 |
| Non-ideal effects | p. 14 |
| MOS transistor mismatch | p. 15 |
| Conductance ratio errors | p. 18 |
| Clock-feedthrough | p. 19 |
| Noise | p. 24 |
| Settling | p. 30 |
| Voltage drop | p. 31 |
| Jitter | p. 31 |
| Summary of non-ideal effects | p. 32 |
| Clock-feedthrough compensation | p. 32 |
| Attenuation techniques | p. 32 |
| Cancellation techniques | p. 33 |
| Algorithmic techniques | p. 36 |
| Fully-differential, feedforward and feedback techniques | p. 37 |
| Adaptive techniques | p. 38 |
| Zero-voltage switching techniques | p. 38 |
| CFT compensation techniques used in this book | p. 39 |
| Current sample-and-hold evolution | p. 39 |
| References | p. 42 |
| Switched-Current Systems | p. 49 |
| Sampled-data filters | p. 49 |
| FIR-filters | p. 49 |
| IIR-filters | p. 50 |
| Miscellaneous filters | p. 53 |
| Design methodology and analysis | p. 53 |
| Influence of SI circuit imperfections | p. 54 |
| A/D Converters | p. 54 |
| Nyquist A/D converters | p. 55 |
| Oversampling [Delta] - [Sigma] A/D converters | p. 59 |
| Influence of SI circuit imperfections | p. 60 |
| References | p. 61 |
| SI Circuit Design Issues | p. 69 |
| Clock-Feedthrough Compensated First-Generation SI Circuit Design | p. 71 |
| Introduction | p. 71 |
| Clock-feedthrough compensation in SI circuits | p. 72 |
| Clock-feedthrough modeling | p. 72 |
| Large-signal CFT error current | p. 73 |
| Complete CFT cancellation | p. 74 |
| Coefficient matching sensitivity | p. 76 |
| Memory cell design options | p. 77 |
| Optimizing an arbitrary goal function | p. 78 |
| Minimizing CFT | p. 79 |
| Experimental results | p. 80 |
| Summary | p. 80 |
| References | p. 81 |
| Sampling Time Uncertainty | p. 83 |
| Introduction | p. 83 |
| Sampling time Uncertainty | p. 84 |
| Reducing sampling time uncertainty | p. 86 |
| Random jitter | p. 86 |
| Signal dependent jitter | p. 87 |
| Summary | p. 89 |
| References | p. 90 |
| Design of Power Supply Wires | p. 91 |
| Introduction | p. 91 |
| Voltage drop on power supply wires | p. 92 |
| Design considerations | p. 94 |
| Quiescent point shift | p. 94 |
| Offset and distortion | p. 95 |
| Summary | p. 96 |
| SI Circuit Layout | p. 97 |
| Introduction | p. 97 |
| Difference between SI and SC circuit layout | p. 97 |
| Floorplanning | p. 99 |
| Layout styles | p. 100 |
| Style I | p. 100 |
| Style II | p. 102 |
| Layout Automation | p. 103 |
| References | p. 105 |
| SI Circuit Implementation Examples | p. 107 |
| A 3.3-V CMOS Wave SI Filter | p. 109 |
| Introduction | p. 109 |
| Discrete-time wave filters | p. 110 |
| Current-mode realization of N-port adaptors | p. 112 |
| Switched-current delay element realization | p. 113 |
| Potential for automatic generation | p. 115 |
| Filter realization | p. 117 |
| Simulation results | p. 118 |
| Experimental results | p. 119 |
| Summary | p. 119 |
| References | p. 120 |
| A 3.3-V CMOS Switched-Current Delta-Sigma Modulator | p. 121 |
| Introduction | p. 121 |
| Modulator structure | p. 122 |
| System level simulations | p. 123 |
| Circuit implementation | p. 124 |
| Experimental results | p. 125 |
| Summary | p. 127 |
| References | p. 127 |
| A 3-V Wideband CMOS Switched-Current A/D-Converter | p. 129 |
| Introduction | p. 129 |
| Switched-current A/D converters | p. 131 |
| RSD A/D converter architecture | p. 132 |
| Circuit implementation | p. 133 |
| Simulation results | p. 136 |
| System level simulations | p. 136 |
| Circuit level simulations | p. 138 |
| Experimental results | p. 140 |
| Performance comparison | p. 144 |
| Summary | p. 147 |
| References | p. 148 |
| A Dual 3-V 32-MS/s CMOS Switched-Current ADC | p. 151 |
| Introduction | p. 151 |
| A/D converter architecture | p. 152 |
| Circuit implementation | p. 153 |
| Experimental results | p. 154 |
| ADC core cell | p. 154 |
| Parallel ADC | p. 156 |
| Summary | p. 158 |
| References | p. 159 |
| Conclusions | p. 161 |
| Noise Integrals | p. 165 |
| Index | p. 167 |
| Table of Contents provided by Syndetics. All Rights Reserved. |
