
Substrate Noise Coupling in Mixed-Signal ASICs
By: Stéphane Donnay (Editor), Georges Gielen (Editor)
Hardcover | 28 February 2003
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324 Pages
24.13 x 16.51 x 1.91
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Industry Reviews
From the reviews:
"This book covers modeling and simulation for the noise from substrate. This book reviews the causes of noise in substrate and possible prevention of the noise. ... As a practicing engineer, I feel that their techniques for noise prevention are legitimate and applicable. This book is worthwhile for IC design engineers. Those engineers that work on integration of analog and digital parts may want to read this book to prevent any malfunctioning ICs." (IEEE Circuits & Devices Magazine, Vol. 20 (5), September/October, 2004)
| Contributors | p. xi |
| Foreword | p. xix |
| Projects in the mixed-signal design cluster | p. xxi |
| Introduction | p. xxv |
| Context | p. xxv |
| Book overview | p. xxvii |
| Technology impact on substrate noise | p. 1 |
| Introduction | p. 1 |
| Substrate physics | p. 4 |
| Resistive effect | p. 4 |
| Capacitive effect | p. 4 |
| Depletion regions | p. 6 |
| Latch-up | p. 7 |
| Parasitic substrate effects | p. 8 |
| Water impact | p. 11 |
| Lightly doped wafer | p. 12 |
| Epitaxial wafer | p. 14 |
| Fabrication processes | p. 17 |
| Surface implant | p. 17 |
| Buried layers | p. 18 |
| Conclusions | p. 19 |
| Substrate noise generation in complex digital systems | p. 23 |
| Introduction | p. 23 |
| Sources of substrate noise | p. 24 |
| Substrate modeling | p. 25 |
| How to measure substrate noise | p. 26 |
| First mixed-signal test chip with simple inverter chains | p. 28 |
| Time-domain substrate noise | p. 30 |
| Dominant noise coupling source analysis | p. 31 |
| Frequency domain substrate noise | p. 33 |
| Second test chip: a 86-Kgate digital filter bank | p. 35 |
| Measurement results | p. 37 |
| Substrate noise analysis | p. 38 |
| Conclusions | p. 42 |
| Modeling and analysis of substrate noise coupling in mixed-signal ICs | p. 47 |
| Introduction | p. 47 |
| Substrate noise analysis methodology | p. 50 |
| Modeling parasitics | p. 51 |
| Device/Well/Interconnect parasitics | p. 52 |
| Package parasitics | p. 52 |
| Substrate parasitics | p. 53 |
| Analysis of substrate noise | p. 55 |
| Analysis of impact of substrate noise | p. 57 |
| Substrate noise analysis data flow | p. 58 |
| A design example | p. 59 |
| Summary | p. 63 |
| SPACE for substrate resistance extraction | p. 65 |
| Introduction | p. 65 |
| Substrate analysis overview | p. 68 |
| Modeling | p. 68 |
| Extraction | p. 70 |
| The Boundary Element Method | p. 72 |
| Introduction | p. 72 |
| Discretization | p. 74 |
| Matrix inversion | p. 75 |
| Results | p. 79 |
| Parametric modeling method | p. 80 |
| Methodology | p. 80 |
| Implementation and results | p. 85 |
| Conclusion | p. 86 |
| Combined BEM/FEM Modeling | p. 86 |
| The SPACE Layout to Circuit Extractor | p. 89 |
| Conclusion | p. 90 |
| Models and parameters for crosstalk simulation | p. 93 |
| Introduction | p. 93 |
| Design methodology | p. 95 |
| Top-down design | p. 95 |
| Bottom-up verification | p. 96 |
| Modeling | p. 97 |
| Parameters | p. 100 |
| Package parasitics | p. 100 |
| On-chip parasitics: capacitances | p. 100 |
| On-chip parasitics: resistances | p. 101 |
| Simulation | p. 106 |
| Validation of the proposed approach | p. 106 |
| Comparison with simulations from the back-annotated netlist | p. 106 |
| Comparison with experimental measurements on a test chip | p. 108 |
| Conclusion | p. 110 |
| High-level simulation of substrate noise generation in complex digital systems | p. 113 |
| Introduction | p. 113 |
| Library characterization | p. 115 |
| Substrate macro model characterization | p. 115 |
| Effect of load and input transition time | p. 118 |
| Gate-level VHDL library extension for monitoring the switching activities | p. 120 |
| Substrate noise simulation | p. 121 |
| Overview of substrate noise simulation | p. 121 |
| Chip-level substrate lumped network | p. 121 |
| Extraction of the noise sources | p. 124 |
| Substrate noise simulation | p. 125 |
| Experimental results | p. 125 |
| Four Bit Counter | p. 125 |
| Multiplier | p. 127 |
| Accuracy of SWAN in comparison with measurements for 86K gate digital ASIC | p. 129 |
| Speed-up of SWAN in comparison with SPICE simulations | p. 130 |
| Conclusions | p. 132 |
| Modeling the impact of digital substrate noise on analog integrated circuits | p. 135 |
| Introduction | p. 135 |
| Overview of substrate noise impact in analog circuits | p. 138 |
| Modeling the digital substrate noise impact on analog circuits | p. 140 |
| Principle of the modeling method | p. 140 |
| Description of the model extraction methodology | p. 142 |
| Illustration and validation of the modeling methodology | p. 143 |
| Measurements of the impact of digital substrate noise on analog designs | p. 151 |
| Digital substrate noise impact on a comparator | p. 151 |
| Experimental test chip and measurement setup | p. 153 |
| Comparator measurement results | p. 155 |
| Impact of substrate noise on an embedded analog-to-digital converter | p. 157 |
| Conclusions | p. 159 |
| Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver | p. 161 |
| Introduction | p. 161 |
| General model of the effect of substrate noise on analog circuits | p. 163 |
| Substrate noise characterization | p. 165 |
| Substrate noise caused by a single digital transition | p. 168 |
| Substrate noise spectra distribution for the digital circuit emulator | p. 171 |
| Noise coupling into the LNA | p. 174 |
| LNA output spectrum | p. 174 |
| Noise coupling mechanism | p. 175 |
| Experimental verification | p. 179 |
| A statistical approach to substrate noise characterization for digital circuits | p. 180 |
| Conclusion | p. 185 |
| A practical approach to modeling silicon-crosstalk in systems-on-silicon | p. 189 |
| Introduction | p. 189 |
| Problem statement | p. 190 |
| Limitations in state-of-the-art approaches to silicon-crosstalk | p. 195 |
| Our strategy | p. 196 |
| Modeling the digital circuitry | p. 196 |
| Modeling the analog circuitry | p. 201 |
| Substrate modeling for low-impedance substrate (0.35[mu] pure CMOS) and overall simulations | p. 201 |
| Substrate modeling (BiCMOS/RFCMOS substrates) | p. 204 |
| Overall simulations | p. 205 |
| Conclusions | p. 207 |
| The reduction of switching noise using CMOS current steering logic | p. 209 |
| Introduction | p. 209 |
| Definitions | p. 210 |
| CSL inverter | p. 210 |
| Static Characteristics | p. 211 |
| Noise Margins | p. 212 |
| Dynamic Characteristics | p. 213 |
| Current Spikes | p. 215 |
| CSL NAND and NOR gates | p. 216 |
| FSCL inverter | p. 217 |
| Static Characteristics | p. 218 |
| Noise Margin | p. 219 |
| Dynamic Characteristics | p. 220 |
| Complex gates in FSCL | p. 222 |
| Experimental comparison between static logic and CSL | p. 223 |
| Switching noise sensing | p. 223 |
| Comparison between CSL and standard static logic in a mixed-mode application | p. 225 |
| Comparative evaluation of CSL, FSCL and conventional static logic | p. 227 |
| Power consumption in CMOS conventional static logic | p. 227 |
| Power consumption in CMOS CSL and FSCL | p. 228 |
| Summary | p. 229 |
| CSL design and layout CAD tools | p. 230 |
| CSL libraries design CAD tool | p. 230 |
| CSL layout generator CAD tool | p. 231 |
| Conclusion | p. 232 |
| Low-noise digital design techniques | p. 233 |
| Introduction | p. 233 |
| Reducing substrate noise generation | p. 235 |
| Supply current transfer function to the substrate | p. 235 |
| Shaping the supply current | p. 236 |
| Changing the supply current transfer function to the substrate | p. 240 |
| Clock tree with different latencies | p. 242 |
| Introduction | p. 242 |
| Clock region assignment | p. 243 |
| Folding of the supply current transients | p. 244 |
| Clock latency optimization | p. 245 |
| Experimental results | p. 245 |
| Measurements to evaluate the low-noise design techniques | p. 248 |
| Overview of the simulated reduction factors for the generated substrate noise | p. 248 |
| Time- and frequency-domain measurements | p. 250 |
| Effect of I/O cells | p. 252 |
| Conclusions | p. 253 |
| How to deal with substrate bounce in analog circuits in epi-type CMOS technology | p. 257 |
| Introduction | p. 257 |
| Substrate noise | p. 258 |
| Problems in analog | p. 260 |
| Strategy for analog | p. 262 |
| Examples | p. 265 |
| Conclusions | p. 268 |
| Reducing substrate bounce in CMOS RF-circuitry | p. 271 |
| Introduction | p. 271 |
| Substrate bounce due to a sigma-delta modulator | p. 274 |
| Guard rings on a low-ohmic substrate | p. 276 |
| Guard rings on a high-ohmic substrate | p. 281 |
| Substrate bounce in an RF system | p. 282 |
| Concluding remarks | p. 286 |
| Table of Contents provided by Ingram. All Rights Reserved. |
ISBN: 9781402073816
ISBN-10: 140207381X
Published: 28th February 2003
Format: Hardcover
Language: English
Number of Pages: 324
Audience: Professional and Scholarly
Publisher: Springer Nature B.V.
Country of Publication: US
Dimensions (cm): 24.13 x 16.51 x 1.91
Weight (kg): 0.72
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