Static Timing Analysis for Nanometer Designs

A Practical Approach

By: J. Bhasker, Shelly Sun

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Hardcover | 6 May 2009

At a Glance

Hardcover
594 Pages

Dimensions(cm)
24.13 x 16.51 x 3.18

Hardcover

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The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts.

The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology.

This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Technology in General Nanotechnology Energy Technology & Engineering Electrical Engineering Computing & I.T.Graphical & Digital Media Applications Computer-Aided Design CAD

Other Editions and Formats

Paperback

Published: 8th September 2011

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Introduction
STA Concepts
Standard Cell Library
Interconnect Parasitics
Delay Calculation
Noise and Crosstalk
Configuring the Environment: Preparing for STA
Timing Verification
Robust Verification
Table of Contents provided by Publisher. All Rights Reserved.

Static Timing Analysis for Nanometer Designs

A Practical Approach

At a Glance

Hardcover

Shipping

How to return your order

Defective items

You Can Find This Book In

Other Editions and Formats

Paperback

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