| Preface | p. xix |
| Acknowledgements | p. xxi |
| Overview | p. 1 |
| Silicon on Insulator--a brief Introduction | p. 1 |
| Circuits and SOI | p. 2 |
| Technology and SOI | p. 3 |
| SOI Materials | p. 5 |
| Silicon on Heteroepitaxial Substrate | p. 5 |
| Silicon-Oxide-Silicon SOI substrates | p. 6 |
| Comparison of SOI and Bulk | p. 11 |
| SOI Technology Advantages | p. 16 |
| Performance | p. 17 |
| Partially and Fully Depleted-SOI | p. 19 |
| Technology Scaling | p. 21 |
| SOI Device Properties | p. 22 |
| Body Effects | p. 23 |
| Body Ties | p. 29 |
| Device Noise | p. 35 |
| Self Heating | p. 36 |
| Components | p. 47 |
| MOS devices | p. 47 |
| Diodes | p. 49 |
| Bipolar Transistors | p. 49 |
| Lateral DMOS | p. 51 |
| Drain Extended Devices | p. 53 |
| Compound High Voltage SOI Structures | p. 56 |
| Passive Components | p. 57 |
| SOI Modeling | p. 63 |
| Modeling Introduction | p. 63 |
| Example SOI spice deck | p. 66 |
| Models | p. 68 |
| Alternative Model Options | p. 70 |
| Layout for SOI | p. 75 |
| Introduction to Layout for SOI components | p. 75 |
| Converting designs from Bulk to SOI | p. 77 |
| Layout for Minimization of Thermal Self Heating Effects | p. 80 |
| Output Stages | p. 83 |
| Static SOI Design | |
| Introduction | p. 85 |
| Decreased Body Effect | p. 87 |
| Gate Leakage | p. 88 |
| Static Inverter Characteristics | p. 89 |
| Body Voltages in SOI Inverters | p. 92 |
| Body Voltage Convergence | p. 94 |
| Noise Margin In Inverters | p. 95 |
| Nand Gate Response | p. 96 |
| Nor Gate response | p. 103 |
| Static OR-AND SOICMOS Circuit | p. 104 |
| XOR Gate response in SOI | p. 107 |
| Ring Oscillator Performance | p. 108 |
| Pass Gate Response | p. 112 |
| History Dependence | p. 117 |
| SOI vs BULK: Performance benefits in Digital Circuits | p. 118 |
| Floating body and hysteresis effect | p. 119 |
| Non Ideal diode characteristics | p. 120 |
| Dynamic SOI Design | |
| Introduction | p. 125 |
| Dynamic Circuit Response | p. 125 |
| Dynamic Circuit Design Considerations | p. 129 |
| Re-ordering and Remapping | p. 130 |
| Logical Remapping | p. 130 |
| Complex Domino | p. 132 |
| No-Race Logic (NORA) | p. 136 |
| Dynamic Noise Suppression | p. 141 |
| Design Issues in Dynamic 2-way NAND Logic | p. 142 |
| Dynamic 2-Way OR Circuit | p. 145 |
| Dynamic Cascade Switch Logic | p. 147 |
| Clocked CMOS | p. 149 |
| Pulse Stretching in Dynamic Circuits | p. 153 |
| Dynamic Wide-OR | p. 157 |
| Non Overlapping Clocks | p. 158 |
| Pass transistor based Non-Overlapping Clocks | p. 159 |
| Low Power SOI Techniques | p. 161 |
| SOI SRAMs | |
| Introduction | p. 181 |
| SRAM Cell structures | p. 182 |
| Design considerations and specifications for SRAM Cells | p. 185 |
| Four Transistor SRAM using Self-body biased MOSFET | p. 187 |
| Basic SOI SRAM Cell operation | p. 189 |
| Cell Stability | p. 197 |
| SRAM Junction and Bit line capacitance | p. 201 |
| Decoders | p. 201 |
| SRAM Architecture | p. 203 |
| Bit Line Related Architecture | p. 205 |
| Sense Amplifiers | p. 206 |
| Mismatches in Sense Amplifiers | p. 220 |
| Mismatch in SRAM Cells | p. 225 |
| SER Issues in SRAMs | p. 227 |
| SOI CMOS Memory Challenges | p. 228 |
| Destructive read-out characteristics of SRAM | p. 229 |
| SOI DRAMs | |
| Introduction | p. 235 |
| DRAM structure and Operation | p. 237 |
| Memory Array | p. 238 |
| DRAM cell storage | p. 241 |
| SOI DRAM Process | p. 244 |
| Influence Of SER on SOI DRAMs | p. 246 |
| Cosmic Ray induced Soft Errors in SOI DRAMs | p. 247 |
| DRAM Refresh and Data Retention | p. 249 |
| High Density DRAMs with Body Contacts | p. 258 |
| Operating Voltage Reduction | p. 259 |
| Sense Amplifier Operation | p. 260 |
| Word Line Boosting | p. 267 |
| Charge pumps and generators | p. 269 |
| Embedded DRAMS in SOI | p. 274 |
| DRAM operation problems | p. 274 |
| SOI DRAM READ Critical Path Body Contacts | p. 275 |
| Synchronous Interface on DRAMs | p. 276 |
| High Speed Modes for Synchronous DRAMs | p. 278 |
| Prefetch Architecture | p. 279 |
| Other Architectures | p. 280 |
| Destructive read out characteristics of DRAM | p. 281 |
| SOI Analog Design | |
| Introduction | p. 289 |
| Body Voltage Regulation | p. 292 |
| Circuit Thermal Coupling Effects | p. 294 |
| Band-gap Designs | p. 295 |
| Charge Pump Circuitry | p. 301 |
| Amplifiers | p. 302 |
| Matching | p. 310 |
| Output Stages / Buffers | p. 311 |
| High Voltage and Power Applications | p. 312 |
| Sample and Hold Circuitry | p. 312 |
| Circuits for RF/Wireless Applications | p. 313 |
| Microwave Applications | p. 324 |
| Voltage Regulation | p. 325 |
| Analog to Digital Converters (ADC) | p. 326 |
| Digital-to-Analog Converters (DAC) | p. 330 |
| Sigma Delta Modulator | p. 331 |
| Interface between Digital and Analog Circuitry | p. 332 |
| Power Amplifiers | p. 333 |
| Sensors and Actuators | p. 333 |
| Global Design Issues | |
| Introduction to Global Design Issues | p. 339 |
| Noise Immunity | p. 341 |
| Latchup Immunity | p. 343 |
| Self Heating | p. 346 |
| Electrostatic Discharge (ESD) | p. 347 |
| Radiation Hard (Rad-Hard) Circuits | p. 349 |
| Reliability | p. 350 |
| Package and Bond wire | p. 355 |
| Low Power Design | |
| Introduction | p. 359 |
| Clocking | p. 360 |
| Options for Low Power | p. 361 |
| Analog Low Voltage Operation | p. 364 |
| Floating Voltage Schemes | p. 364 |
| System Performance | p. 366 |
| System Power Management | p. 367 |
| Instruction Set Architecture | p. 368 |
| Reduction of Voltage below 3.3V | p. 368 |
| SOI in Development | |
| SOI Technology Roadmap | p. 371 |
| Device Enhancements | p. 371 |
| Quantum Devices | p. 373 |
| Stacked SOI | p. 373 |
| Reduced Temperature Operation | p. 374 |
| High Temperature Operation | p. 374 |
| New Circuit Designs for SOI | p. 375 |
| Internet Sites (issue 1.0) | p. 381 |
| Trade Mark / Technology Information (issue 1.0) | p. 382 |
| Index | p. 383 |
| About the Authors | p. 392 |
| Table of Contents provided by Syndetics. All Rights Reserved. |