SOI Circuit Design Concepts

By: Kerry Bernstein, Norman J. Rohrer

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Hardcover | 1 January 2000

At a Glance

Hardcover
244 Pages

Dimensions(cm)
23.5 x 15.88 x 1.91

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Market demand for microprocessor performance has motivated continued scaling of CMOS through a succession of lithography generations. Quantum mechanical limitations to continued scaling are becoming readily apparent. Partially Depleted Silicon-on-Insulator (PD-SOI) technology is emerging as a promising means of addressing these limitations. It also introduces additional design complexity which must be well understood. This text first introduces the student or practising engineer to SOI device physics and its fundamental idiosyncrasies. It then walks the reader through realizations of these mechanisms which are observed in common high-speed microprocessor designs. Rules of thumb and comparisons to conventional bulk CMOS are offered to guide implementation. SOI's ultimate advantage, however, may lie in the unique circuit topologies it supports; a number of these novel new approaches is also described.

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Electronic Devices & Materials Semi-Conductors & Super-Conductors Computing & I.T.Computer Science Systems Analysis & Design Microprocessors Circuits & Components Energy Technology & Engineering

Electrical Engineering

Preface
The Time for SOI
Technology Scaling in VLSI
The End of Moore's Law?
The Case for PD-SOI
Summary
SOI Device Structures
Introduction
Wafer Fabrication
Patterning SOI Regions
Transistor Structures
Diodes
Resistors
Decoupling Capacitors
Summary
SOI Device Electrical Properties
Introduction
SOI MOSFET's Junction Diode
Impact Ionization
Floating Body Effects
SOI MOSFET Modeling
Insulator-Related Effects
Composite Responses
Summary
Static Circuit Design Response
Introduction
Parameters of Interest to Circuit Designers
First Switch vs. Second Switch
First Switch vs. Steady State
Static Circuit Response to SOI
Passgate Circuit Response
Summary
Dynamic Circuit Design Considerations
Introduction
Dynamic Circuit Response
Preferred Dynamic Design Practices
Keeping Dynamic SOI Problems in Perspective
Soft Errors in Dynamic Logic
Dynamic Logic Performance
Conclusions
SRAM Cache Design Considerations
Overview
Writing a Cell
Reading a Cell
Cell Stability and Cell Bias
SRAM Noise Considerations
Precharging Circuitry
Soft Error Upsets
Array Test in PD-SOI
Summary
Specialized Function Circuits in SOI
Introduction
Timing Elements
Latch Response in SOI
Input/Output Circuitry
Electro-Static Discharge (ESD) Protection
Summary
Global Chip Design Considerations
Introduction
Temperature Effects
Noise Immunity
Power Consumption
Power Supply Issues Noise
System Performance
SOI Timing Variability
Summary
Future Opportunities in SOI
Introduction
Floating body Effect Suppression
DTCMOS
DGCMOS
3-Dimensional SOI
Future Scaling Opportunities
Summary
About the Authors
Index
Table of Contents provided by Publisher. All Rights Reserved.

SOI Circuit Design Concepts

At a Glance

Hardcover

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How to return your order

Defective items

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