SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

By: Krishnendu Chakrabarty

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Hardcover | 30 September 2002

At a Glance

Hardcover
212 Pages

Edition Type
New edition

Dimensions(cm)
26.04 x 19.68 x 1.27

Hardcover

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System-on-a-Chip (SOC) integrated circuits composed of embedded cores are now commonplace. Nevertheless, there remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design and manufacturing capabilities. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. In addition, long interconnects, high density, and high-speed designs lead to new types of faults involving crosstalk and signal integrity.

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is an edited work containing thirteen contributions that address various aspects of SOC testing.

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is a valuable reference for researchers and students interested in various aspects of SOC testing.

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Non-Fiction Computing & I.T.Computer Science Computer Architecture & Logic Design Engineering & Technology Energy Technology & Engineering Electrical Engineering Electronics & Communications Engineering Electronics Engineering Circuits & Components Electronic Devices & Materials Graphical & Digital Media Applications

Foreword	p. v
Preface	p. vii
Overview: On IEEE P1500's Standard for Embedded Core Test	p. 1
Test Planning, Access and Scheduling
An Integrated Framework for the Design and Optimization of SOC Test Solutions	p. 21
On Concurrent Test of Core-Based SOC Design	p. 37
A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm	p. 51
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs	p. 71
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing	p. 91
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch	p. 111
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores	p. 123
Test Data Compression
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor	p. 139
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test	p. 151
Interconnect, Crosstalk and Signal Integrity
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores	p. 165
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs	p. 175
On-Chip Clock Faults' Detector	p. 191
Table of Contents provided by Ingram. All Rights Reserved.

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation

At a Glance

Hardcover

Shipping

How to return your order

Defective items

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