SOC Design Methodologies

IFIP TC10 / WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01) December 3-5, 2001, Montpellier, France

By: Michel Robert (Editor), Bruno Rouzeyre (Editor), Christian Piguet (Editor)

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Hardcover | 31 July 2002

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496 Pages

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The 11 th IFIP International Conference on Very Large Scale Integration, in Montpellier, France, December 3-5,2001, was a great success. The main focus was about IP Cores, Circuits and System Designs & Applications as well as SOC Design Methods and CAD. This book contains the best papers (39 among 70) that have been presented during the conference. Those papers deal with all aspects of importance for the design of the current and future integrated systems. System on Chip (SOC) design is today a big challenge for designers, as a SOC may contain very different blocks, such as microcontrollers, DSPs, memories including embedded DRAM, analog, FPGA, RF front-ends for wireless communications and integrated sensors. The complete design of such chips, in very deep submicron technologies down to 0.13 mm, with several hundreds of millions of transistors, supplied at less than 1 Volt, is a very challenging task if design, verification, debug and industrial test are considered. The microelectronic revolution is fascinating; 55 years ago, in late 1947, the transistor was invented, and everybody knows that it was by William Shockley, John Bardeen and Walter H. Brattein, Bell Telephone Laboratories, which received the Nobel Prize in Physics in 1956. Probably, everybody thinks that it was recognized immediately as a major invention.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computing & I.T.Computer Science Energy Technology & Engineering Electrical Engineering Automatic Control Engineering Medicine Medicine in General

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Published: 6th March 2013

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Preface	p. ix
Conference Committees	p. xiii
Architecture for Signal & Image Processing
Two ASIC for Low and Middle Levels of Real Time Image Processing	p. 3
64 x 64 Pixels General Purpose Digital Vision Chip	p. 15
A Vision System on Chip for Industrial Control	p. 27
Fast Recursive Implementation of the Gaussian Filter	p. 39
Dynamically Re-configurable Architectures
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals	p. 51
Dynamically Reconfigurable Architectures for Digital Signal Processing Applications	p. 63
Reconfigurable Architecture Using High Speed FPGA	p. 75
CAD Tools
Design Technology for Systems-on-Chip	p. 87
Distributed Collaborative Design over Cave2 Framework	p. 97
High Performance Java Hardware Engine and Software Kernel for Embedded Systems	p. 109
An Object-Oriented Methodology for Modeling the Precise Behavior of Processor Architectures	p. 121
Interconnect Capacitance Modelling in a VDSM CMOS Technology	p. 133
IP Design & Reuse
Abstract Communication Model and Automatic Interface generation for IP integration in Hardware/Software Co-design	p. 145
An Evolutionary Approach for Pareto-optimal Configurations in SOC Platforms	p. 157
Design of a Branch-Based Carry-Select Adder IP Portable in 0.25 [mu]m Bulk and Silicon-On-Insulator CMOS Technologies	p. 169
High Level Design Methodologies
A Standardized Co-simulation Backbone	p. 181
Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory	p. 193
Power Issues
Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model	p. 205
Power Consumption Model for the DSP OAK Processor	p. 217
Design for Specific Constraints
Integration of Robustness in the Design of a Cell	p. 229
Impact of Technology Spreading on MEMS design Robustness	p. 241
Architectures
A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation	p. 253
Design Considerations of a Low-Complexity, Low-Power Integer Turbo Decoder	p. 265
Low Power, Low Voltage
Low-Voltage Embedded-RAM Technology: Present and Future	p. 277
Low-Voltage 0,25 [mu]m CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors	p. 289
Gate Sizing for Low Power Design	p. 301
Timing Issues
Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems	p. 313
Feasible Delay Bound Definition	p. 325
Advance in Mixed Signal
CMOS Mixed-signal Circuits Design on a Digital Array Using Minimum Transistors	p. 337
A VHDL-AMS Case Study: The Incremental Design of an Efficient 3[superscript rd] Generation MOS Model of a Deep Sub Micron Transistor	p. 349
Verification & Validation
Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths	p. 361
Functional Test Generation using Constraint Logic Programming	p. 375
Test
An Industrial Approach to Core-Based System Chip Testing	p. 389
Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme	p. 401
Random Adjacent Sequences: An Efficient Solution for Logic BIST	p. 413
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST	p. 425
Built-in Test of Analog Non-Linear Circuits in a SOC Environment	p. 437
Sensors
Design of a Fast CMOS APS Imager for High Speed Laser Detections	p. 449
Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing	p. 461
Authors Index	p. 473
Keywords Index	p. 475
Table of Contents provided by Ingram. All Rights Reserved.

SOC Design Methodologies

IFIP TC10 / WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on-Chip (VLSI-SOC'01) December 3-5, 2001, Montpellier, France

At a Glance

Hardcover

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Defective items

You Can Find This Book In

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Paperback

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