Foreword.
From the Early Days of CMOS to Today.
Signal Integrity: A Problem for Design and CAD Engineers.
Preface.
Acknowledgments.
Signal Integrity Effects in Systme-on-Chip Designs - A
Designer's Perspective.
Part 1: Interconnect Crosstalk.
Harmony: Static Noise Analysis of Deep Submicron Digital
Integrated Circuits.
FastCap: A Multipole Accelerated 3-D Capacitance Extraction
Program.
Efficient Coupled Noise Estimation for On-Chip
Interconnects.
Switching Window Computation for Static Timing Analysis in
Presence of Crosstalk Noise.
Digital Sensitivity: Predicting Signal Interaction using
Functional Analysis.
Crosstalk Reduction for VLSI.
Noise-aware Repeater Insertion and Wire Sizing For On-Chip
Interconnect Hierarchical Moment-Matching.
Post Global Routing Crosstalk Synthesis.
Minimum Crosstalk Channel Routing.
Reducing Cross-Coupling among Interconnect Wires in
Deep-Submicron Datapath Design.
A Postprocessing Algorithm for Crosstalk-driven Wire
Perturbation.
Noise in Digital Dynamic CMOS Circuits.
Design of Dynamic Circuits with Enhanced Noise Tolerance.
Coupling-Driven Signal Encoding Scheme for Low-Power Interface
Design.
High Frequency Simulation and Characterization of Advanced
Copper Interconnects.
Static Noise Analysis for Digital Integrated Circuits in
Partially-Depleted Silicon-On-Insulator Technology.
Synthesis of CMOS Domino Circuits for Charge Sharing
Alleviation.
Part 2: Inductance Effects.
On-Chip Wiring Design Challenges for Gigahertz Operation.
IC Analyses Including Extracted Inductance Models.
FASTHENRY: A Multipole-Accelerated 3-D Inductance Extraction
Program.
Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction.
On-Chip Inductance Modeling and Analysis.
How to Efficiently Capture On-Chip Inductance Effects:
Introducing a New Circuit Element K.
Figures of Merit to Characterize the Importance of On-Chip
Inductance.
Layout-Techniques for Minimizing On-Chip Interconnect Self
Inductance.
A Twisted-Bundle Layout Structure for Minimizing Inductive
Coupling Noise.
Part 3: Power Grid and Distribution Noise.
Full-Chip Verification of UDSM Designs.
Power Supply Noise in Future IC's: A Crystal Ball Reading.
A Floorplan-based Planning Methodology for Power and Clock
Distribution in ASICs.
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI
Chip Design.
Analysis of Performance Impact Caused by Power Supply Noise in
Deep Submicron Devices.
Full-Chip Signal Interconnect Analysis for Electromigration
Reliability.
Power Dissipation Analysis and Optimization of Deep Submicron
CMOS Digital Circuits.
Simulation and Optimization of the Power Distribution Network in
VLSI Circuits.
Design Strategies and Decoupling Techniques for Reducing the
Effects of Electrical Interference in Mixed-Mode IC's.
Design and Analysis of Power Distribution Networks in Power PC
Microprocessors.
Modeling the Power and Ground Effects of BGA Packages.
Effects of Power/Ground Via Distribution on the Power/Ground
Performance of C4/BGA Packages.
Power Distribution Fidelity of Wirebond Compared to Flip Chip
Devices in Grid Array Packages.
Forming Damped LRC Parasitic Circuits in Simultaneously Switched
CMOS Output Buffers.
Part 4: Substrate Noise.
Experimental Results and Modeling Techniques for Substrate Noise
in Mixed-Signal Integrated Circuits.
Principles of Substrate Crosstalk Generation in CMOS
Circuits.
Experimental Comparison of Substrate Noise Coupling Using
Different Wafer Types.
Modeling and Analysis of Substrate Coupling in Integrated
Circuits.
Fast Methods for Extraction and Sparsification of Substrate
Coupling.
SUBWAVE: A Methodology for Modeling Digital Substrate Noise
Injection in Mixed-Signal ICs.
Substrate Modeling and Lumped Substrate Resistance Extraction
for CMOS ESD/Latchup Circuit Simulation.
Analysis of Ground-Bounce Induced Substrate Noise Coupling in a
Low Resistive Bulk Epitaxial Process: Design Strategies to Minimize
Noise Effects on a Mixed-Signal Chip.
A Methodology for Measurement and Characterization of Substrate
Noise in High Frequency Circuits.
Measurement of Digital Noise in Mixed-Signal Integrated
Circuits.
Effects of Substrate Resistances on LNA Performance and a
Bondpad Structure for Reducing the Effects in a Silicon Bipolar
Technology.
A Study of Oscillator Jitter Due to Supply and Substrate
Noise.
CMOS Technology Characterization for Analog and RF Design.
Noise Reduction Is Crucial to Mixed-Signal ASIC Design Success
(Parts I & II).
Author Index.
Subject Index.
About the Editor.
