PREFACE xi
PART I INDIVIDUAL RF BLOCKS 1
1 LNA (LOW NOISE AMPLIFIER) 3
1.1 Introduction 3
1.2 Single-Ended Single Device LNA 4
1.3 Single-Ended Cascode LNA 41
1.4 LNA with AGC (Automatic Gain Control) 66
2 MIXERS 75
2.1 Introduction 75
2.2 Passive Mixers 78
2.3 Active Mixers 88
2.4 Design Schemes 99
3 DIFFERENTIAL PAIRS 113
3.1 Why Differential Pairs? 113
3.2 Can DC Offset be Blocked by a Capacitor? 121
3.3 Fundamentals of Differential Pairs 126
3.4 CMRR (Common Mode Rejection Ratio) 138
4 RF BALUN 155
4.1 Introduction 155
4.2 Transformer Baluns 158
4.3 LC Baluns 181
4.4 Micro Strip Line Baluns 191
4.5 Mixed Types of Baluns 195
5 TUNABLE FILTERS 219
5.1 Tunable Filters in Communication Systems 219
5.2 Coupling Between Two Tank Circuits 221
5.3 Circuit Description 227
5.4 Effect of Second Coupling 228
5.5 Performance 232
6 VCO (VOLTAGE-CONTROLLED OSCILLATOR) 237
6.1 "Three-Point" Type Oscillators 237
6.2 Other Single-Ended Oscillators 244
6.3 VCO and PLL 249
6.4 Design Example of a Single-Ended VCO 259
6.5 Differential VCO and Quad Phases VCO 269
7 POWER AMPLIFIERS (PA) 277
7.1 Classifications of Power Amplifiers 277
7.2 Single-Ended PA Design 283
7.3 Single-Ended PA-IC Design 287
7.4 Push-Pull PA Design 288
7.5 PA with Temperature Compensation 312
7.6 PA with Output Power Control 315
7.7 Linear PA 317
PART II DESIGN TECHNOLOGIES AND SCHEMES 323
8 DIFFERENT METHODOLOGY BETWEEN RF AND DIGITAL CIRCUIT DESIGN 325
8.1 Controversy 325
8.2 Differences between RF and Digital Blocks in a Communication System 329
8.3 Conclusion 332
8.4 Notes for High-Speed Digital Circuit Design 332
9 VOLTAGE AND POWER TRANSPORTATION 334
9.1 Voltage Delivered from a Source to a Load 334
9.2 Power Delivered from a Source to a Load 342
9.3 Impedance Conjugate Matching 350
9.4 Additional Effects of Impedance Matching 362
10 IMPEDANCE MATCHING IN NARROW-BAND CASE 377
10.1 Introduction 377
10.2 Impedance Matching by Means of Return Loss Adjustment 380
10.3 Impedance Matching Network Built of One Part 385
10.4 Impedance Matching Network Built of Two Parts 391
10.5 Impedance Matching Network Built of Three Parts 402
10.6 Impedance Matching When ZS or ZL Is Not 50 Ω 408
10.7 Parts in an Impedance Matching Network 413
11 IMPEDANCE MATCHING IN A WIDE-BAND CASE 447
11.1 Appearance of Narrow- and Wide-Band Return Loss on a Smith Chart 447
11.2 Impedance Variation Due to Insertion of One Part per Arm or per Branch 453
11.3 Impedance Variation Due to the Insertion of Two Parts per Arm or per Branch 462
11.4 Impedance Matching in IQ Modulator Design for a UWB System 468
11.5 Discussion of Wide-band Impedance Matching Networks 495
12 IMPEDANCE AND GAIN OF A RAW DEVICE 501
12.1 Introduction 501
12.2 Miller Effect 503
12.3 Small Signal Model of a Bipolar Transistor 507
12.4 Bipolar Transistor with CE (Common Emitter) Confi guration 511
12.5 Bipolar Transistor with CB (Common Base) Confi guration 526
12.6 Bipolar Transistor with CC (Common Collector) Confi guration 539
12.7 Small Signal Model of a MOSFET Transistor 547
12.8 Similarity between Bipolar and MOSFET Transistors 552
12.9 MOSFET Transistor with CS (Common Source) Configuration 563
12.10 MOSFET Transistor with CG (Common Gate) Configuration 573
12.11 MOSFET Transistor with CD (Common Drain) Configuration 579
12.12 Comparison of Bipolar and MOSFET Transistors in Various Configurations 584
13 IMPEDANCE MEASUREMENT 588
13.1 Introduction 588
13.2 Scale and Vector Voltage Measurement 589
13.3 Direct Impedance Measurement by Network Analyzer 593
13.4 Alternative Impedance Measurement by Network Analyzer 603
13.5 Impedance Measurement with the Assistance of a Circulator 607
14 GROUNDING 611
14.1 Implications of Grounding 611
14.2 Possible Grounding Problems Hidden in a Schematic 613
14.3 Imperfect or Inappropriate Grounding Examples 614
14.4 "Zero" Capacitor 620
14.5 Quarter Wavelength of Micro Strip Line 632
15 EQUIPOTENTIALITY AND CURRENT COUPLING ON THE GROUND SURFACE 651
15.1 Equipotentiality on the Ground Surface 651
15.2 Forward and Return Current Coupling 664
15.3 PCB or IC Chip with Multi-metallic Layers 674
16 RFIC (RADIO FREQUENCY INTEGRATED CIRCUIT) AND SOC (SYSTEM ON CHIP) 684
16.1 Interference and Isolation 684
16.2 Shielding for an RF Module by a Metallic Shielding Box 687
16.3 Strong Desirability to Develop RFIC 688
16.4 Interference Going Along an IC Substrate Path 689
16.5 Solution for Interference Coming from the Sky 695
16.6 Common Grounding Rules for an RF Module and RFIC Design 696
16.7 Bottlenecks in RFIC Design 697
16.8 Prospect of SOC 705
16.9 What Is Next? 706
17 MANUFACTURABILITY OF PRODUCT DESIGN 718
17.1 Introduction 718
17.2 Implication of 6Ï Design 720
17.3 Approaching 6Ï Design 724
17.4 Monte Carlo Analysis 728
PART III RF SYSTEM ANALYSIS 743
18 MAIN PARAMETERS AND SYSTEM ANALYSIS IN RF CIRCUIT DESIGN 745
18.1 Introduction 745
18.2 Power Gain 747
18.3 Noise 758
18.4 Non-Linearity 773
18.5 Other Parameters 803
18.6 Example of RF System Analysis 804
Appendices 807
References 814
INDEX 817
