Resource Efficient LDPC Decoders : From Algorithms to Hardware Architectures - Aziz

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Resource Efficient LDPC Decoders

From Algorithms to Hardware Architectures

By: Aziz, Chandrasetty

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Paperback | 5 December 2017 | Edition Number 1

At a Glance

Paperback
190 Pages

Dimensions(cm)
22.86 x 18.42 x 1.27

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This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms. The reader will learn:

Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation
How to reduce computational complexity and power consumption using computer aided design techniques
All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs

Provides extensive treatment of LDPC decoding algorithms and hardware implementations
Gives a systematic guidance, giving a basic understanding of LDPC codes and decoding algorithms and providing practical skills in implementing efficient LDPC decoders in hardware
Companion website containing C-Programs and MATLAB models for simulating the algorithms, and Verilog HDL codes for hardware modeling and synthesis

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