Quantifying and Exploring the Gap Between FPGAs and ASICs

By: Ian Kuon, Jonathan Rose

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Hardcover | 5 October 2009

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194 Pages

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24.2 x 16.5 x 1.7

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Field-programmable gate arrays (FPGAs), which are pre-fabricated, programmable digital integrated circuits (ICs), provide easy access to state-of-the-art integrated circuit process technology, and in doing so, democratize this technology of our time. This book is about comparing the qualities of FPGA - their speed performance, area and power consumption, against custom-fabricated ICs, and exploring ways of mitigating their de ciencies. This work began as a question that many have asked, and few had the resources to answer - how much worse is an FPGA compared to a custom-designed chip? As we dealt with that question, we found that it was far more dif cult to answer than we anticipated, but that the results were rich basic insights on fundamental understandings of FPGA architecture. It also encouraged us to nd ways to leverage those insights to seek ways to make FPGA technology better, which is what the second half of the book is about. While the question "How much worse is an FPGA than an ASIC?" has been a constant sub-theme of all research on FPGAs, it was posed most directly, some time around May 2004, by Professor Abbas El Gamal from Stanford University to us - he was working on a 3D FPGA, and was wondering if any real measurements had been made in this kind of comparison. Shortly thereafter we took it up and tried to answer in a serious way.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computing & I.T.Computer Science Computer Architecture & Logic Design Graphical & Digital Media Applications Computer Hardware

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Paperback

Published: 3rd September 2014

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Introduction	p. 1
Measuring the FPGA to ASIC Gap	p. 2
Navigating the Gap	p. 3
Organization	p. 4
Background	p. 5
FPGA Architecture	p. 5
Logic Block Architecture	p. 5
Routing Architecture	p. 9
Heterogeneity	p. 12
FPGA Circuit Design	p. 13
FPGA Transistor Sizing	p. 16
FPGA Assessment Methodology	p. 17
FPGA CAD Flow	p. 17
Area Model	p. 18
Performance Measurement	p. 20
Automated Transistor Sizing	p. 20
Static Transistor Sizing	p. 21
Dynamic Sizing	p. 23
Hybrid Approaches to Sizing	p. 23
FPGA-Specific Sizing	p. 24
FPGA to ASIC Gap	p. 24
Measuring the Gap	p. 27
Comparison Methodology	p. 28
Benchmark Circuit Selection	p. 28
FPGA CAD Flow	p. 31
ASIC CAD Flow	p. 32
ASIC Synthesis	p. 32
ASIC Placement and Routing	p. 35
Extraction and Timing Analysis	p. 36
Comparison Metrics	p. 36
Area	p. 36
Delay	p. 37
Power	p. 37
Measurement Results	p. 39
Area	p. 40
Delay	p. 49
Dynamic Power Consumption	p. 55
Static Power Consumption	p. 58
Summary	p. 61
Automated Transistor Sizing for FPGAs	p. 63
Uniqueness of FPGA Transistor Sizing Problem	p. 64
Programmability	p. 64
Repetition	p. 64
Optimization Tool Inputs	p. 65
Logical Architecture Parameters	p. 65
Electrical Architecture Parameters	p. 66
Optimization Objective	p. 67
Optimization Metrics	p. 68
Area Model	p. 68
Performance Modelling	p. 71
Optimization Algorithm	p. 73
Phase 1: Switch-Level Transistor Models	p. 74
Phase 2: Sizing with Accurate Models	p. 79
Quality of Results	p. 82
Comparison with Past Routing Optimizations	p. 82
Comparison with Past Logic Block Optimization	p. 84
Comparison to Exhaustive Search	p. 89
Optimizer Run Time	p. 90
Summary	p. 90
Navigating the Gap Using Architecture and Process Technology Scaling	p. 91
Area and Performance Measurement Methodology	p. 92
Performance Measurement	p. 92
Area Measurement	p. 94
Impact of Logical Architectures on Area and Performance	p. 95
Impact of Process Technology Scaling on Area and Performance	p. 98
Summary	p. 101
Navigating the Gap using Transistor Sizing	p. 103
Transistor-Sizing Trade-offs	p. 104
Definition of "Interesting" Trade-offs	p. 106
Trade-Offs with Transistor Sizing and Architecture	p. 109
Impact of Elasticity Threshold Factor	p. 111
Logical Architecture Trade-offs	p. 112
LUT Size	p. 113
Cluster Size	p. 114
Segment Length	p. 115
Circuit Structure Trade-offs	p. 115
Buffer Positioning	p. 116
Multiplexer Implementation	p. 118
Trade-offs and the Gap	p. 122
Comparison with Commercial Families	p. 124
Summary	p. 125
Conclusions and Future Work	p. 127
Knowledge Gained	p. 127
Future Potential Research Directions	p. 128
Measuring the Gap	p. 128
Navigating the Gap	p. 130
Concluding Remarks	p. 131
FPGA to ASIC Comparison Details	p. 133
Benchmark Information	p. 133
FPGA to ASIC Comparison Data	p. 133
Representative Delay Weighting	p. 141
Benchmark Statistics	p. 141
Representative Delay Weights	p. 144
Multiplexer Implementations	p. 147
Multiplexer Designs	p. 147
Evaluation of Multiplexer Designs	p. 149
Architectures Used for Area and Delay Range Investigation	p. 155
Logical Architecture to Transistor Sizing Process	p. 159
References	p. 165
Index	p. 179
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Quantifying and Exploring the Gap Between FPGAs and ASICs

At a Glance

Hardcover

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How to return your order

Defective items

You Can Find This Book In

Other Editions and Formats

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