Principles of Asynchronous Circuit Design

A Systems Perspective

By: Jens SparsÃ¸ (Editor), Steve Furber (Editor)

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Hardcover | 31 December 2001

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364 Pages

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Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors.
The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

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Published: 29th October 2010

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Preface	p. xi
Acknowledgments	p. xiii
Foreword	p. xv
Asynchronous circuit design--A tutorial
Introduction	p. 3
Why consider asynchronous circuits?	p. 3
Aims and background	p. 4
Clocking versus handshaking	p. 5
Outline of Part I	p. 8
Fundamentals	p. 9
Handshake protocols	p. 9
Bundled-data protocols	p. 9
The 4-phase dual-rail protocol	p. 11
The 2-phase dual-rail protocol	p. 13
Other protocols	p. 13
The Muller C-element and the indication principle	p. 14
The Muller pipeline	p. 16
Circuit implementation styles	p. 17
4-phase bundled-data	p. 18
2-phase bundled data (Micropipelines)	p. 19
4-phase dual-rail	p. 20
Theory	p. 23
The basics of speed-independence	p. 23
Classification of asynchronous circuits	p. 25
Isochronic forks	p. 26
Relation to circuits	p. 26
Test	p. 27
Summary	p. 28
Static data-flow structures	p. 29
Introduction	p. 29
Pipelines and rings	p. 30
Building blocks	p. 31
A simple example	p. 33
Simple applications of rings	p. 35
Sequential circuits	p. 35
Iterative computations	p. 35
FOR, IF, and WHILE constructs	p. 36
A more complex example: GCD	p. 38
Pointers to additional examples	p. 39
A low-power filter bank	p. 39
An asynchronous microprocessor	p. 39
A fine-grain pipelined vector multiplier	p. 40
Summary	p. 40
Performance	p. 41
Introduction	p. 41
A qualitative view of performance	p. 42
Example 1: A FIFO used as a shift register	p. 42
Example 2: A shift register with parallel load	p. 44
Quantifying performance	p. 47
Latency, throughput and wavelength	p. 47
Cycle time of a ring	p. 49
Example 3: Performance of a 3-stage ring	p. 51
Final remarks	p. 52
Dependency graph analysis	p. 52
Example 4: Dependency graph for a pipeline	p. 52
Example 5: Dependency graph for a 3-stage ring	p. 54
Summary	p. 56
Handshake circuit implementations	p. 57
The latch	p. 57
Fork, join, and merge	p. 58
Function blocks--The basics	p. 60
Introduction	p. 60
Transparency to handshaking	p. 61
Review of ripple-carry addition	p. 64
Bundled-data function blocks	p. 65
Using matched delays	p. 65
Delay selection	p. 66
Dual-rail function blocks	p. 67
Delay insensitive minterm synthesis (DIMS)	p. 67
Null Convention Logic	p. 69
Transistor-level CMOS implementations	p. 70
Martin's adder	p. 71
Hybrid function blocks	p. 73
MUX and DEMUX	p. 75
Mutual exclusion, arbitration and metastability	p. 77
Mutual exclusion	p. 77
Arbitration	p. 79
Probability of metastability	p. 79
Summary	p. 80
Speed-independent control circuits	p. 81
Introduction	p. 81
Asynchronous sequential circuits	p. 81
Hazards	p. 82
Delay models	p. 83
Fundamental mode and input-output mode	p. 83
Synthesis of fundamental mode circuits	p. 84
Signal transition graphs	p. 86
Petri nets and STGs	p. 86
Some frequently used STG fragments	p. 88
The basic synthesis procedure	p. 91
Example 1: a C-element	p. 92
Example 2: a circuit with choice	p. 92
Example 2: Hazards in the simple gate implementation	p. 94
Implementations using state-holding gates	p. 96
Introduction	p. 96
Excitation regions and quiescent regions	p. 97
Example 2: Using state-holding elements	p. 98
The monotonic cover constraint	p. 98
Circuit topologies using state-holding elements	p. 99
Initialization	p. 101
Summary of the synthesis process	p. 101
Petrify: A tool for synthesizing SI circuits from STGs	p. 102
Design examples using Petrify	p. 104
Example 2 revisited	p. 104
Control circuit for a 4-phase bundled-data latch	p. 106
Control circuit for a 4-phase bundled-data MUX	p. 109
Summary	p. 113
Advanced 4-phase bundled-data protocols and circuits	p. 115
Channels and protocols	p. 115
Channel types	p. 115
Data-validity schemes	p. 116
Discussion	p. 116
Static type checking	p. 118
More advanced latch control circuits	p. 119
Summary	p. 121
High-level languages and tools	p. 123
Introduction	p. 123
Concurrency and message passing in CSP	p. 124
Tangram: program examples	p. 126
A 2-place shift register	p. 126
A 2-place (ripple) FIFO	p. 126
GCD using while and if statements	p. 127
GCD using guarded commands	p. 128
Tangram: syntax-directed compilation	p. 128
The 2-place shift register	p. 129
The 2-place FIFO	p. 130
GCD using guarded repetition	p. 131
Martin's translation process	p. 133
Using VHDL for asynchronous design	p. 134
Introduction	p. 134
VHDL versus CSP-type languages	p. 135
Channel communication and design flow	p. 136
The abstract channel package	p. 138
The real channel package	p. 142
Partitioning into control and data	p. 144
Summary	p. 146
The VHDL channel packages	p. 148
The abstract channel package	p. 148
The real channel package	p. 150
Balsa - An Asynchronous Hardware Synthesis System
An introduction to Balsa	p. 155
Overview	p. 155
Basic concepts	p. 156
Tool set and design flow	p. 159
Getting started	p. 159
A single-place buffer	p. 161
Two-place buffers	p. 163
Parallel composition and module reuse	p. 164
Placing multiple structures	p. 165
Ancillary Balsa tools	p. 166
Makefile generation	p. 166
Estimating area cost	p. 167
Viewing the handshake circuit graph	p. 168
Simulation	p. 168
The Balsa language	p. 173
Data types	p. 173
Data typing issues	p. 176
Control flow and commands	p. 178
Binary/unary operators	p. 181
Program structure	p. 181
Example circuits	p. 183
Selecting channels	p. 190
Building library components	p. 193
Parameterised descriptions	p. 193
A variable width buffer definition	p. 193
Pipelines of variable width and depth	p. 194
Recursive definitions	p. 195
An n-way multiplexer	p. 195
A population counter	p. 197
A Balsa shifter	p. 200
An arbiter tree	p. 202
A simple DMA controller	p. 205
Global registers	p. 205
Channel registers	p. 206
DMA controller structure	p. 207
The Balsa description	p. 211
Arbiter tree	p. 211
Transfer engine	p. 212
Control unit	p. 213
Large-Scale Asynchronous Designs
Descale	p. 221
Introduction	p. 222
VLSI programming of asynchronous circuits	p. 223
The Tangram toolset	p. 223
Handshake technology	p. 225
GCD algorithm	p. 226
Opportunities for asynchronous circuits	p. 231
Contactless smartcards	p. 232
The digital circuit	p. 235
The 80C51 microcontroller	p. 236
The prefetch unit	p. 239
The DES coprocessor	p. 241
Results	p. 243
Test	p. 245
The power supply unit	p. 246
Conclusions	p. 247
An Asynchronous Viterbi Decoder	p. 249
Introduction	p. 249
The Viterbi decoder	p. 250
Convolution encoding	p. 250
Decoder principle	p. 251
System parameters	p. 253
System overview	p. 254
The Path Metric Unit (PMU)	p. 256
Node pair design in the PMU	p. 256
Branch metrics	p. 259
Slot timing	p. 261
Global winner identification	p. 262
The History Unit (HU)	p. 264
Principle of operation	p. 264
History Unit backtrace	p. 264
History Unit implementation	p. 267
Results and design evaluation	p. 269
Conclusions	p. 271
Acknowledgement	p. 272
Further reading	p. 272
Processors	p. 273
An introduction to the Amulet processors	p. 274
Amulet1 (1994)	p. 274
Amulet2e (1996)	p. 275
Amulet3i (2000)	p. 275
Some other asynchronous microprocessors	p. 276
Processors as design examples	p. 278
Processor implementation techniques	p. 279
Pipelining processors	p. 279
Asynchronous pipeline architectures	p. 281
Determinism and non-determinism	p. 282
Dependencies	p. 288
Exceptions	p. 297
Memory - a case study	p. 302
Sequential accesses	p. 302
The Amulet3i RAM	p. 303
Cache	p. 307
Larger asynchronous systems	p. 310
System-on-Chip (DRACO)	p. 310
Interconnection	p. 310
Balsa and the DMA controller	p. 312
Calibrated time delays	p. 313
Production test	p. 314
Summary	p. 315
Epilogue	p. 317
References	p. 319
Index	p. 333
Table of Contents provided by Syndetics. All Rights Reserved.

Principles of Asynchronous Circuit Design

A Systems Perspective

At a Glance

Hardcover

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