| Foreword | p. xiii |
| Preface | p. xv |
| Introduction | p. 1 |
| Introduction to MMICs | p. 2 |
| The History of MMICs | p. 3 |
| The MMIC Advantage | p. 6 |
| Basic Design Process | p. 7 |
| References | p. 8 |
| Component Technology and Foundry Choice | p. 11 |
| Active Components | p. 12 |
| Substrate Material | p. 12 |
| Transistor Type | p. 14 |
| Transistor Response Versus Frequency | p. 30 |
| Passive Components | p. 31 |
| Diodes | p. 31 |
| Transmission Lines | p. 31 |
| Resistors | p. 42 |
| Capacitors | p. 44 |
| Inductors | p. 46 |
| Metal Layer Interconnects | p. 49 |
| Bond-pads | p. 49 |
| Substrate Vias | p. 50 |
| Questions | p. 50 |
| References | p. 52 |
| Foundry Use and Economics | p. 57 |
| Using a Foundry | p. 57 |
| Agreements and Discussions | p. 57 |
| Delivery of Design Data | p. 59 |
| Circuit Design | p. 59 |
| Design Review | p. 60 |
| Wafer Fabrication | p. 60 |
| Test and Delivery | p. 61 |
| Economics | p. 61 |
| MMIC Production Costs | p. 61 |
| Defect Densities | p. 62 |
| References | p. 64 |
| Simulation and Component Models | p. 65 |
| Simulation | p. 66 |
| The s-parameters | p. 66 |
| Component Characterization | p. 69 |
| Model Development | p. 71 |
| Linear Simulation | p. 74 |
| Nonlinear Simulation | p. 74 |
| 2D, 2.5D, and 3D Electromagnetic Simulation | p. 75 |
| Passive Component Models | p. 76 |
| Capacitors | p. 76 |
| Inductors | p. 77 |
| Resistors | p. 78 |
| Vias | p. 79 |
| Transmission-Line Discontinuities | p. 79 |
| Active Component Models | p. 82 |
| FET Model | p. 83 |
| HBT Model | p. 84 |
| Questions | p. 84 |
| References | p. 85 |
| Design | p. 89 |
| Impedance Matching and the Smith Chart | p. 90 |
| Matching | p. 90 |
| Smith Chart | p. 92 |
| Converting Impedance to Reflection Coefficient | p. 95 |
| Converting Impedance to Admittance | p. 96 |
| Deriving the Conjugate Impedance | p. 96 |
| Transforming a Load Impedance Along a Lossless Transmission Line | p. 97 |
| Addition of Series Reactive and Shunt Susceptance Lumped Elements | p. 99 |
| T and Pi Matching Circuits | p. 103 |
| Curves of Constant Q-factor | p. 104 |
| Circles of Constant Performance | p. 105 |
| Passive Elements | p. 108 |
| Open Circuit and Short Circuit Stubs | p. 108 |
| Radial Stubs | p. 109 |
| Couplers, Splitters, and Combiners | p. 110 |
| Baluns | p. 122 |
| Filters | p. 123 |
| Antennas | p. 124 |
| Amplifiers | p. 125 |
| Initial Considerations | p. 126 |
| Small-Signal Amplifiers | p. 132 |
| Power Amplifiers | p. 147 |
| Oscillators | p. 188 |
| Oscillation Principles | p. 189 |
| Mixers | p. 194 |
| MMIC Mixers | p. 196 |
| Switches | p. 207 |
| Phase Shifters | p. 210 |
| Reflective Phase Shifters | p. 210 |
| Loaded-Line Phase Shifters | p. 211 |
| Switched-Delay-Line Phase Shifters | p. 211 |
| Switched-Filter Phase Shifters | p. 211 |
| Switched-Path Attenuators | p. 213 |
| Circuits with Digital Application | p. 214 |
| Prescalers | p. 214 |
| Logarithmic Amplifiers | p. 215 |
| Darlington Pair Amplifiers | p. 216 |
| Millimeter-Wave Circuits | p. 216 |
| High-Frequency Effects | p. 217 |
| Component Choice | p. 221 |
| Simulation Issues | p. 228 |
| Yield Improvement | p. 231 |
| What Is the MMIC Yield? | p. 232 |
| Yield-Improvement Techniques | p. 234 |
| Questions | p. 246 |
| References | p. 250 |
| Layout | p. 261 |
| Layout Files | p. 262 |
| Circuit Layout Process | p. 264 |
| Layout Checking | p. 267 |
| Layout Design Rules | p. 267 |
| Design Rule Checking | p. 269 |
| Electrical Rule Checking | p. 270 |
| Layout Versus Schematic | p. 270 |
| Reverse Engineering | p. 270 |
| Visual Checking | p. 270 |
| Chip Arraying | p. 270 |
| Chip Identifiers | p. 271 |
| Arraying Guidelines | p. 273 |
| Mask Manufacture | p. 274 |
| Layout Examples | p. 274 |
| Questions | p. 277 |
| References | p. 277 |
| Processing Technology | p. 279 |
| Substrate Material Growth | p. 280 |
| Wafer Production | p. 283 |
| Surface Layers | p. 283 |
| Photolithography | p. 285 |
| Typical MMIC Photolithographic Steps | p. 288 |
| Device Isolation | p. 290 |
| Ohmic Contacts | p. 291 |
| Gate Contacts | p. 293 |
| First Interconnect Metal | p. 296 |
| High-Dielectric-Constant Layer | p. 296 |
| Resistive Metal | p. 298 |
| Low-Dielectric-Constant Layer | p. 298 |
| Second Interconnect Metal | p. 299 |
| Dielectric Encapsulation and Saw/Scribe Lane Definition | p. 301 |
| Wafer Thinning | p. 302 |
| Through-Substrate Vias | p. 304 |
| Back-Face Metal | p. 305 |
| Chip Separation | p. 306 |
| Quality Assurance | p. 306 |
| Questions | p. 308 |
| References | p. 309 |
| Test | p. 313 |
| Process Control and Monitoring (PCM) | p. 313 |
| The dc Test and Stability Problems | p. 314 |
| RF Testing and Calibration | p. 315 |
| Questions | p. 319 |
| References | p. 320 |
| Answers to Questions | p. 323 |
| p. 323 |
| p. 324 |
| p. 324 |
| p. 328 |
| p. 329 |
| p. 330 |
| Glossary | p. 331 |
| About the Author | p. 341 |
| Index | p. 343 |
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