Practical Formal Methods for Hardware Design

By: C. Delgado Kloos, Carlos Delgado Kloos (Editor), Werner Damm (Editor)

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Formal methods for hardware design still find limited use in industry. Yet current practice has to change to cope with decreasing design times and increasing quality requirements. This research report presents results from the Esprit project FORMAT (formal methods in hardware verification) which involved the collaboration of the enterprises Siemens, Italtel, Telefonica I+D, TGI, and AHL, the research institute OFFIS, and the universities of Madrid and Passau. The work presented involves advanced specification languages for hardware design that are intuitive to the designer, like timing diagrams and state based languages, as well as their relation to VHDL and formal languages like temporal logic and a process-algebraic calculus. The results of experimental tests of the tools are also presented.

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Non-Fiction Computing & I.T.Computer Science Computer Architecture & Logic Design Computer Hardware Storage Media & Peripherals Systems Analysis & Design Computer Programming & Software Development Personal Computers Computer Networking & Communications EDI Electronic Data Interchange Engineering & Technology

Electronics & Communications Engineering Electronics Engineering Gardening

Preface
Introduction	p. 1
Design Methodology for Complex VLSI Devices	p. 7
Specification Languages	p. 23
Verification Flow	p. 52
Synthesis Flow	p. 81
Application of a Formal Verification Toolset to the Design of Integrated Circuits in an Industrial Environment	p. 99
Italtel Application of the FORMAT Design Flow	p. 132
Siemens Industrial Experience	p. 159
The FORMAT Model Checker	p. 175
Reasoning	p. 184
VHDL Formal Modeling and Analysis	p. 217
Synthesis Techniques	p. 229
Generating VHDL Code from LOTOS Descriptions	p. 266
Table of Contents provided by Blackwell. All Rights Reserved.

Practical Formal Methods for Hardware Design

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