| Acknowledgement | p. V |
| Introduction | p. 1 |
| Carrier Physics and Junction Electrostatics | p. 3 |
| Introduction | p. 3 |
| Crystal Structure and Energy Bands | p. 3 |
| Carrier Concentration and Fermi Level | p. 10 |
| Intrinsic Semiconductor | p. 13 |
| Extrinsic Semiconductor | p. 15 |
| Carrier Transport | p. 17 |
| Carrier Drift | p. 18 |
| Carrier Diffusion | p. 23 |
| Resistivity | p. 24 |
| Bandgap Reduction | p. 25 |
| Carrier Recombination | p. 29 |
| Carrier Lifetime | p. 34 |
| Carrier Lifetime Control | p. 36 |
| Auger Recombination | p. 44 |
| Basic Equations in Semiconductor | p. 45 |
| p-n Junction Electrostatics | p. 47 |
| Junction Breakdown Phenomena | p. 51 |
| Abrupt p+-n Junction | p. 55 |
| Linearly Graded Junction | p. 57 |
| Punchthrough Phenomenon | p. 59 |
| Junction Termination | p. 62 |
| Cylindrical Junction | p. 63 |
| Spherical Junction | p. 65 |
| Floating Field Ring | p. 66 |
| Etched Contour Termination | p. 68 |
| Bevelled Edge Termination | p. 69 |
| Field Plate | p. 72 |
| Junction Termination Extension | p. 72 |
| SIPOS (Semi-insulating Polycrystalline Silicon) Termination | p. 73 |
| Summary | p. 74 |
| Bipolar Junction Diode | p. 78 |
| Introduction | p. 78 |
| Basic Junction Diode Theory | p. 81 |
| Forward Conduction | p. 81 |
| Short-base Diode | p. 83 |
| Junction Capacitance | p. 85 |
| High-Voltage p+-n--n+ Diode | p. 87 |
| Forward Conduction | p. 88 |
| Reverse Blocking | p. 95 |
| Temperature Effect | p. 96 |
| Schottky Barrier Diode | p. 103 |
| Forward Conduction | p. 106 |
| Reverse Blocking | p. 109 |
| Ohmic Contact | p. 111 |
| GaAs and SiC Power Diodes | p. 114 |
| Switching Characteristics | p. 119 |
| Turn-on Transient | p. 120 |
| Turn-off Transient | p. 123 |
| MPS (Merged p-i-n/Schottky) Diode | p. 127 |
| Smart-Power Integrated Synchronous Rectifier | p. 128 |
| Summary | p. 136 |
| Power Metal-Oxide-Semiconductor Field-Effect Transistor | p. 141 |
| Introduction | p. 141 |
| Basic MOS Physics | p. 142 |
| Flat-band State | p. 144 |
| Accumulation State | p. 144 |
| Depletion State | p. 144 |
| Inversion State | p. 146 |
| MOS Capacitance | p. 147 |
| Threshold Voltage | p. 149 |
| Static Characteristics | p. 151 |
| Linear Region Operation | p. 154 |
| Saturation Region Operation | p. 157 |
| Mobility Degradation | p. 158 |
| Forward Blocking | p. 159 |
| Switching Characteristics | p. 159 |
| Turn-on Transient | p. 159 |
| Turn-off Transient | p. 162 |
| Gate Charge | p. 165 |
| High-frequency Operation | p. 166 |
| Parasitic Body Diode | p. 167 |
| dv/dt Limit | p. 167 |
| Dummy-Gated Structure | p. 169 |
| Folded Gate Structure | p. 171 |
| Lateral Radio Frequency (RF) Power MOSFET | p. 172 |
| Graded Gate | p. 173 |
| Stepped Lateral Double Diffusion | p. 174 |
| Partial Silicon-on-Insulator Platform | p. 175 |
| Partial SOI Platform Formation | p. 177 |
| Parallel and Series Operations | p. 180 |
| Gate Drive Circuits | p. 183 |
| Insulated-Gate Bipolar Transistor | p. 189 |
| Introduction | p. 189 |
| Device Structure and Current-Voltage Characteristics | p. 191 |
| Forward Conduction Characteristics | p. 193 |
| Output Resistance | p. 197 |
| Switching Characteristics | p. 198 |
| Latch-up | p. 200 |
| Temperature Effects | p. 203 |
| Series and Parallel Operations | p. 204 |
| Device Operations under Soft-switching | p. 205 |
| Dual-Gate IGBT for ZV Soft-Switching | p. 207 |
| Lateral IGBT Structure | p. 209 |
| Integrated Current Sensor | p. 211 |
| Fabrication Aspects | p. 215 |
| Performances | p. 216 |
| Safe Operating Area | p. 221 |
| Overcurrent Protection | p. 222 |
| Vertical IGBT Fabrication Process | p. 229 |
| Related MOS-Bipolar Structures | p. 230 |
| Emitter Switched Thyristor (EST) | p. 230 |
| Base-Resistance-Controlled Thyristor (BRT) | p. 238 |
| Injection-Enhanced Insulated-Gate Bipolar Transistor (IEGT) | p. 243 |
| MOS-Controlled Thyristor (MCT) | p. 243 |
| Superjunction Structures | p. 248 |
| Introduction | p. 248 |
| The Unipolar Ideal Silicon Limit | p. 249 |
| The Superjunction Structure | p. 252 |
| SJ Electric Field Profiles | p. 257 |
| Charge Imbalance | p. 259 |
| Fabrication Technologies | p. 259 |
| Practical SJ Performance | p. 263 |
| The Practical Concentration Equation | p. 274 |
| Practical SJ Performance Equation | p. 276 |
| Polysilicon Flanked VDMOS (PF VDMOS) | p. 277 |
| Oxide Bypassed (OB)SJ MOSFET | p. 280 |
| Graded Doping in Drift Region | p. 288 |
| Tunable Oxide Bypassed MOSFETs | p. 290 |
| Gradient Oxide Bypassed (GOB) Structure | p. 297 |
| Lateral Superjunction Power MOSFET | p. 301 |
| Device Process Technology | p. 304 |
| Fabrication and Modeling of Power Devices | p. 310 |
| Unit Process Steps | p. 310 |
| Lithography | p. 310 |
| Etching | p. 313 |
| Deposition | p. 314 |
| Oxidation | p. 315 |
| Ion Implantation | p. 318 |
| Epitaxy | p. 323 |
| Diffusion | p. 323 |
| Basic Models for the Simulation of Unit Process Steps | p. 326 |
| Thermal Oxidation Models | p. 326 |
| Diffusion Models | p. 328 |
| Ion Implantation Models | p. 329 |
| Optical Lithography | p. 330 |
| Etching | p. 332 |
| Deposition | p. 333 |
| Advances in the Processes for Power Devices | p. 333 |
| Modifications to Improve Gate Oxide Reliability and Breakdown Performance | p. 333 |
| Use of Selective Epitaxial Growth for Performance Enhancement | p. 336 |
| Practical Case Studies in Power Devices | p. 340 |
| Case Study I | p. 340 |
| Process Integration to Implement PFVDMOS Device | p. 341 |
| Simulation and Process Parameter Determination of PFVDMOS Device | p. 344 |
| Experimental Results | p. 358 |
| Case Study 2 | p. 373 |
| 100 V TOBUMOS Fabrication | p. 374 |
| Simulation on 100V TOBUMOS | p. 375 |
| Process Flow and Cross-Sections | p. 377 |
| Key Precautions in TOBUMOS Fabrication | p. 386 |
| Device Structure and Mask Layout Design | p. 390 |
| Mask Floorplan and Splits for 100V TOBUMOS Fabrication | p. 394 |
| 100V TOBUMOS Measurement Results and Discussions | p. 396 |
| Investigations for Off-State Failure | p. 403 |
| Measurement Results on New Modified TOBUMOS Fabrication | p. 407 |
| Index | p. 411 |
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