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Power Aware Design Methodologies - Massoud Pedram

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Power Aware Design Methodologies

By: Massoud Pedram, Jan M. Rabaey

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Hardcover | 30 June 2002

At a Glance

Hardcover
548 Pages

Dimensions(cm)
23.5 x 15.88 x 3.18

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$329.00

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Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control.

The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful.

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You Can Find This Book In

Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Energy Technology & Engineering Electrical Engineering Power Generation & Distribution Computing & I.T.Computer Hardware Computer Science Computer Architecture & Logic Design

Computer Programming & Software Development Programming & Scripting Languages

Contributors	p. xvii
Preface	p. xix
Introduction	p. 1
Introduction	p. 1
Sources of Power Consumption	p. 2
Low-Power versus Power-Aware Design	p. 2
Power Reduction Mechanisms in CMOS Circuits	p. 3
Power Reduction Techniques in Microelectronic Systems	p. 4
Book Organization and Overview	p. 5
Summary	p. 7
CMOS Device Technology Trends for Power-Constrained Applications	p. 9
Introduction	p. 9
CMOS Technology Summary	p. 11
Current CMOS Device Technology	p. 11
ITRS Projections	p. 13
Scaling Principles and Difficulties	p. 15
General Scaling	p. 16
Characteristic Scale Length	p. 18
Limits to Scaling	p. 20
Power-constained Scaling Limits	p. 29
Optimizing V[subscript DD] and V[subscript T]	p. 29
Optimizing Gate Insulator Thickness and Gate Length - the Optimal End to Scaling	p. 30
Discussion of the Optimizations	p. 33
Exploratory Technology	p. 35
Body- or Back-Gate Bias	p. 35
Strained Si	p. 36
Fully-Depleted SOI	p. 38
Double-gate FET Structures	p. 40
Low Temperature Operation for High Performance	p. 44
Summary	p. 45
Low Power Memory Design	p. 51
Introduction	p. 51
Flash Memories	p. 52
Flash Memory Cell Operation and Control Schemes	p. 55
Circuits Used in Flash Memories	p. 63
Ferroelectric Memory	p. 74
Basic Operation of FeRAM	p. 74
Low Voltage FeRAM Design	p. 77
Embedded DRAM	p. 82
Advantages of Embedded DRAM	p. 82
Low Voltage Embedded DRAM Design	p. 83
Summary	p. 85
Low-Power Digital Circuit Design	p. 91
Introduction	p. 91
Low Voltage Technologies	p. 92
Variable V[subscript DD] and V[subscript T]	p. 93
Dual V[subscript DD]'s	p. 96
Multiple V[subscript DD]'s and V[subscript T]'s	p. 98
Low Voltage SRAM	p. 106
Low Switching-Activity Techniques	p. 110
Low Capacitance Technologies	p. 118
Summary	p. 118
Low Voltage Analog Design	p. 121
Introduction	p. 122
Fundamental Limits to Low Power Consumption	p. 122
Practical Limitations for Achieving the Minimum Power Consumption	p. 123
Implications of Reduced Supply Voltage	p. 124
Speed-power-accuracy Trade-off in High Speed ADC's	p. 126
High-speed ADC Architecture	p. 126
Models for Matching in Deep-submicron Technologies	p. 129
Impact of Voltage Scaling on Trade-off in High-speed ADC's	p. 136
Slew Rate Dominated Circuits vs. Settling Time Dominated Circuits	p. 143
Solutions for Low Voltage ADC Design	p. 145
Technological Modifications	p. 145
System Level	p. 146
Architectural Level	p. 146
Comparison with Published ADC's	p. 147
Summary	p. 148
Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip	p. 151
Introduction	p. 151
Power Consumption in VLSI Chips	p. 151
Power Consumption of Clocking System in VLSI Chips	p. 152
High-Performance Flip-Flops	p. 155
Low-Power Flip-Flops	p. 156
Master-Slave Latch Pairs	p. 157
Statistical Power Reduction Flip-Flops	p. 158
Small-Swing Flip-Flops	p. 160
Double-Edge Triggered Flip-Flops	p. 162
Low-Swing Clock Double-Edge Triggered Flip-Flop	p. 165
Comparisons of Simulation Results	p. 170
More on Clocking Power-Saving Methodologies	p. 171
Clock Gating	p. 172
Embedded Logic in Flip-Flops	p. 173
Clock Buffer (Repeater) and Tree Design	p. 173
Potential Issues in Multi-GHz SoCs in VDSM Technology	p. 174
Comparison of Power-Saving Approaches	p. 174
Summary	p. 176
Power Optimization by Datapath Width Adjustment	p. 181
Introduction	p. 181
Power Consumption and Datapath Width	p. 183
Datapath Width and Area	p. 183
Energy Consumption and Datapath Width	p. 185
Dynamic Adjustment of Datapath Width	p. 186
Bit-Width Analysis	p. 187
Datapath Width Adjustment on a Soft-core Processor	p. 188
Case Studies	p. 193
ADPCM Decoder LSI	p. 193
MPEG-2 AAC Decoder	p. 194
MPEG-2 Video Decoder Processors	p. 195
Quality-Driven Design	p. 196
Summary	p. 198
Energy-Efficient Design of High-Speed Links	p. 201
Introduction	p. 201
Overview of Link Design	p. 203
Figures of Merit	p. 204
Transmitter	p. 206
Receiver	p. 210
Clock Synthesis and Timing Recovery	p. 212
Putting It Together	p. 214
Approaches for Energy Efficiency	p. 215
Parallelism	p. 215
Adaptive Power-Supply Regulation	p. 218
Putting It Together	p. 222
Examples	p. 222
Supply-Regulated PLL and DLL Design	p. 223
Adaptive-Supply Serial Links	p. 228
Low-Power Area-Efficient Hi-Speed I/O Circuit Techniques	p. 232
Putting It Together	p. 235
Summary	p. 236
System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing	p. 241
Introduction	p. 241
System-level Modeling and Design Exploration	p. 242
The SAN Modeling Paradigm	p. 245
The SAN Model Construction	p. 246
Performance Model Evaluation	p. 248
Case Study: Power-performance of the MPEG-2 Video Decoder Application	p. 249
System Specification	p. 249
Application Modeling	p. 250
Platform Modeling	p. 251
Mapping	p. 252
Results and Discussion	p. 253
Performance Results	p. 254
Power Results	p. 256
Microarchitecture-level Power Modeling	p. 257
Efficient Processor Design Exploration for Low Power	p. 261
Efficient Microarchitectural Power Simulation	p. 262
Design Exploration Trade-offs	p. 265
Implications of Application Profile on Energy-aware Computing	p. 268
On-the-fly Energy Optimal Configuration Detection and Optimization	p. 269
Energy Profiling in Hardware	p. 269
On-the-fly Optimization of the Processor Configuration	p. 270
Selective Dynamic Voltage Scaling	p. 270
Effectiveness of Microarchitecture Resource Scaling	p. 271
Comparison with Static Throttling Methods	p. 272
Summary	p. 273
Tools and Techniques for Integrated Hardware-Software Energy Optimizations	p. 277
Introduction	p. 277
Power Modeling	p. 279
Design of Simulators	p. 281
A SimOS-Based Energy Simulator	p. 282
Trimaran-based VLIW Energy Simulator	p. 284
Hardware-software Optimizations: Case Studies	p. 286
Studying the Impact of Kernel and Peripheral Energy Consumption	p. 286
Studying the Impact of Compiler Optimizations	p. 289
Studying the Impact of Architecture Optimizations	p. 291
Summary	p. 292
Power-Aware Communication Systems	p. 297
Introduction	p. 298
Where Does the Energy Go in Wireless Communications	p. 299
Electronic and RF Energy Consumption in Radios	p. 299
First-order Energy Model for Wireless Communication	p. 302
Power consumption in Short-range Radios	p. 302
Power Reduction and Management for Wireless Communications	p. 304
Lower Layer Techniques	p. 305
Dynamic Power Management of Radios	p. 305
More Lower-layer Energy-speed Control Knobs	p. 315
Energy-aware Medium Access Control	p. 317
Higher Layer Techniques	p. 319
Network Topology Management	p. 319
Energy-aware Data Routing	p. 329
Summary	p. 332
Power-Aware Wireless Microsensor Networks	p. 335
Introduction	p. 335
Node Energy Consumption Characteristics	p. 338
Hardware Architecture	p. 338
Digital Processing Energy	p. 339
Radio Transceiver Energy	p. 341
Power Awareness Through Energy Scalability	p. 343
Dynamic Voltage Scaling	p. 343
Ensembles of Systems	p. 345
Variable Radio Modulation	p. 346
Adaptive Forward Error Correction	p. 349
Power-aware Communication	p. 355
Low-Power Media Access Control Protocol	p. 355
Minimum Energy Multihop Forwarding	p. 359
Clustering and Aggregation	p. 361
Distributed Processing through System Partitioning	p. 363
Node Prototyping	p. 365
Hardware Architecture	p. 366
Measured Energy Consumption	p. 369
Future Directions	p. 369
Summary	p. 370
Circuit and System Level Power Management	p. 373
Introduction	p. 373
System-level Power Management Techniques	p. 377
Greedy Policy	p. 377
Fixed Time-out Policy	p. 378
Predictive Shut-down Policy	p. 378
Predictive Wake-up Policy	p. 379
Stochastic Methods	p. 379
Component-level Power Management Techniques	p. 386
Dynamic Power Minimization	p. 387
Leakage Power Minimization	p. 398
Summary	p. 408
Tools and Methodologies for Power Sensitive Design	p. 413
Introduction	p. 413
The Design Automation View	p. 414
Power Consumption Components	p. 415
Different Types of Power Tools	p. 417
Power Tool Data Requirements	p. 418
Different Types of Power Measurements	p. 426
Transistor Level Tools	p. 427
Transistor Level Analysis Tools	p. 428
Transistor Level Optimization Tools	p. 428
Transistor Level Characterization and Modeling Tools	p. 429
Derivative Transistor Level Tools	p. 430
Gate-level Tools	p. 431
Gate-Level Analysis Tools	p. 432
Gate-Level Optimization Tools	p. 432
Gate-Level Modeling Tools	p. 435
Derivative Gate-Level Tools	p. 436
Register Transfer-level Tools	p. 437
RTL Analysis Tools	p. 438
RTL Optimization Tools	p. 440
Behavior-level Tools	p. 440
Behavior-Level Analysis Tools	p. 441
Behavior-Level Optimization Tools	p. 442
System-level tools	p. 442
A Power-sensitive Design Methodology	p. 443
Power-Sensitive Design	p. 444
Feedback vs. Feed Forward	p. 444
A View to The Future	p. 447
Summary	p. 447
Reconfigurable Processors--the Road to Flexible Power-aware Computing	p. 451
Introduction	p. 451
Platform-Based DEsign	p. 452
Opportunities for energy minimization	p. 454
Voltage as a Design Variable	p. 455
Eliminating Architectural Waste	p. 455
Programmable Architectures--an Overview	p. 456
Architecture Models	p. 457
Homogeneous and Heterogeneous Architectures	p. 460
Agile Computing Systems (Heterogeneous Compute Systems-on-a-chip)	p. 461
The Berkeley Pleiades Platform [10]	p. 462
Concept	p. 462
Architecture	p. 463
Communication Network	p. 465
Benchmark Example: The Maia Chip [10]	p. 466
Architectural Innovations Enable Circuit-level Optimizations	p. 469
Dynamic Voltage Scaling	p. 469
Reconfigurable Low-swing Interconnect Network	p. 470
Summary	p. 471
Energy-efficient System-level Design	p. 473
Introduction	p. 473
Systems on Chips and Their Design	p. 474
SOC Case Studies	p. 477
Emotion Engine	p. 477
MPEG4 Core	p. 479
Single-chip Voice Recorder	p. 482
Design of Memory Systems	p. 484
On-chip Memory Hierarchy	p. 485
Explorative Techniques	p. 487
Memory Partitioning	p. 488
Extending the Memory Hierarchy	p. 489
Bandwidth Optimization	p. 490
Design of Interconnect Networks	p. 491
Signal Transmission on Chip	p. 492
Network Architectures and Control Protocols	p. 493
Energy-efficient Design: Techniques and Examples	p. 494
Software	p. 498
System Software	p. 499
Application Software	p. 502
Summary	p. 510
Index	p. 517
Table of Contents provided by Ingram. All Rights Reserved.

Power Aware Design Methodologies

At a Glance

Hardcover

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