Power-Aware Architecting

The complexity of embedded systems-on-a-chip is rapidly growing. Different experts are involved in the design process: application software designers, programmable core architects, on-chip communication engineers, analog and digital designers, deep sub micron specialists and process engineers. In order to arrive at an optimum implementation compromises are needed across boundaries of the different domains of expertise.

Therefore, the authors of Power-Aware Architecting take the point of view of the system architect who is a generalist rather than an expert. He is responsible for the definition of a high level architecture, which is globally optimal. Finding an optimum requires a proper balance between area, performance and last but not least energy consumption. The challenge is not only the size of the design space but also the fact that the most important decisions are taken during the early design phases. The advantage of an early decision is that the impact on area, performance and energy consumption is large. But the disadvantage is that the available information is often limited, incomplete and inaccurate. The task of the system architect is to take the correct early decisions despite the uncertainties.

Power-Aware Architecting provides a systematic way to support the system architect in this job. Therefore, an iterative system-level design approach is defined where iterations are based on fast and accurate estimations or predictions of area, performance and energy consumption. This method is illustrated with a concrete real life example of multi-carrier communication. This book is the result of a Ph.D. thesis, which is part of the UbiCom project at Delft University of Technology. I strongly recommend it to any engineer, expert of specialist, who is interested in designing embedded systems-on-a-chip.

Jef van Meerbergen
Professor Eindhoven University of Technology
Fellow Philips Research Eindhoven