On-Line Testing for VLSI

By: Michael Nicolaidis (Editor), Yervant Zorian (Editor), Dhiraj Pradhan (Editor)

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Hardcover | 30 April 1998

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168 Pages

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27.94 x 20.32 x 3.81

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Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs.
On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties.
On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.

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Published: 6th December 2010

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Foreword
Introduction
On-Testing for VLSI-A Compendium of Approaches
Self-Checking Design
On-Line Fault Monitoring
Efficient Totally Self-Checking Shifter Design
A New Design Method for Self-Checking Unidirectional Combinational Circuits
Concurrent Delay Detection in Duplication Systems
Self-Checking Checkers
Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters
Self-Testing Embedded Two-Rail Checkers
On-Line Monitoring of Reliability Indicators
Thermal Monitoring of Self-Checking Systems
Integrated Temperature Sensors for On-Line Thermal Monitoring of Microelectronics Structures
Clocked Dosimeter Compatible Digital CMOS
Built-In Self-Test
Design of Scalable Hardware Test Generators for On-Line BIST
Mixed Mode BIST Using Embedded Processors
A BIST Scheme for Non-Volatile Memories
Fault Tolerant Systems
On-Line Fault Resilience through Gracefully Degradable ASICs
Delivering Dependable Telecommunication Services Using Off-the-Shelf System Components
Table of Contents provided by Publisher. All Rights Reserved.

On-Line Testing for VLSI

At a Glance

Hardcover

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How to return your order

Defective items

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Other Editions and Formats

Paperback

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