Network Processor Design

Issues and Practices, Volume 2

By: Mark A. Franklin (Editor), Patrick Crowley (Editor), Haldun Hadimioglu (Editor)

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Paperback | 6 February 2007 | Edition Number 2

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484 Pages

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Responding to ever-escalating requirements for performance, flexibility, and economy, the networking industry has opted to build products around network processors. To help meet the formidable challenges of this emerging field, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers to discuss latest research in the architecture, design, programming, and use of these devices. This series of volumes contains not only the results of the annual workshops but also specially commissioned material that highlights industry's latest network processors.

Like its predecessor volume, Network Processor Design: Principles and Practices, Volume 2 defines and advances the field of network processor design. Volume 2 contains 20 chapters written by the field's leading academic and industrial researchers, with topics ranging from architectures to programming models, from security to quality of service.

Describes current research at UNC Chapel Hill, University of Massachusetts, George Mason University, UC Berkeley, UCLA, Washington University in St. Louis, Linkopings Universitet, IBM, Kayamba Inc., Network Associates, and University of Washington.
Reports the latest applications of the technology at Intel, IBM, Agere, Motorola, AMCC, IDT, Teja, and Network Processing Forum.

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Network Processor Design: Issues and Practics, Volume 2
Preface
Network Processors: Themes and Challenges
Design Principles
A Programmable Scalable Platform for Next Generation Networking
Power Considerations in Network Processor Design
Worst-Case Execution Time Estimation for Hardware-assisted Multithreaded Processors
Multiprocessor Scheduling in Processor-based Router Platforms: Issues and Ideas
A Massively Multithreaded Packet Processor
Exploring Trade-offs in Performance and Programmability of Processing Element Topologies for Network Processors
Packet Classification and Termination in a Protocol Processor
NP-Click: A Programming Model for the Intel IXP1200
NEPAL: A Framework for Efficiently Structuring Applications for Network Processors
Efficient and Faithful Performance Modeling for Network-Processor Based System Designs
High-speed Legitimacy-based DDoS Packet Filtering with Network Processors: A Case Study and Implementation on the Intel IXP1200
Directions in Packet Classification for Network Processors
Practices
Implementing High-performance, High-value Traffic Management Using Agere Network Processor Solutions
AMCC - nPcoreTM "NISC" Architecture
Adaptable Badwidth Allocation for QoS Support in Network Processors
IDT - Network Search Engine with QDRTM LA-1 Interface
Implementing Voice over AAL2 on a Network Processor
Implementing QoS Mechanisms on the Motorola C-Port C-5e Network Processor
A C-based Programming Language for Multiprocessor Network SoC Architectures
Table of Contents provided by Publisher. All Rights Reserved.

Network Processor Design

Issues and Practices, Volume 2

At a Glance

Paperback

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