| Preface | p. ix |
| Acknowledgments | p. xi |
| Introduction | p. 1 |
| Design Flow Overview | p. 7 |
| Design Levels | p. 7 |
| Top-down System Design | p. 9 |
| Bottom-up Verification | p. 11 |
| Simulation Tools in System Design | p. 15 |
| Use of Simulation Tools within the Design Flow | p. 15 |
| Specific Simulation Algorithms of RF Simulators | p. 17 |
| Criteria of the Simulator Selection | p. 21 |
| Internet Resources for Simulation Tools | p. 23 |
| System Level Modeling | p. 25 |
| System Level Simulation | p. 25 |
| Simulation Technology of System Level Simulators | p. 26 |
| Complex Baseband Simulation | p. 27 |
| Principle | p. 27 |
| Example for baseband simulation | p. 30 |
| Restrictions and advantages of baseband modeling | p. 30 |
| Model Libraries for System Simulation | p. 31 |
| Creation of Own Primitive and Hierarchical Models | p. 33 |
| SPW modeling example | p. 33 |
| VHDL-AMS for Block Level Simulation | p. 39 |
| Introduction | p. 39 |
| VHDL-AMS Standardization | p. 40 |
| A Simple Block Level Example - Analog PLL | p. 41 |
| Mathematical models of basic blocks | p. 42 |
| Structural description of the PLL circuit in VHDL-AMS | p. 44 |
| VHDL-AMS description of basic blocks | p. 47 |
| Summary | p. 50 |
| Introduction to VHDL-AMS | p. 51 |
| Aim of this Introduction | p. 51 |
| Repetition of Basics of VHDL 1076-1993 | p. 52 |
| Design units | p. 52 |
| Logical libraries and compilation of design units | p. 56 |
| Concurrent statements | p. 60 |
| A simple pure digital example - divider | p. 65 |
| Conservative Systems Description | p. 66 |
| Network analysis problem | p. 67 |
| Nature, terminal and branch quantity declarations | p. 71 |
| Simultaneous statements and free quantity declarations | p. 78 |
| Example of a conservative system - A-law companding | p. 85 |
| Attributes in VHDL-AMS | p. 88 |
| Example - higher order lowpass filter | p. 103 |
| Description of Nonconservative Systems | p. 105 |
| Mixed-Signal Simulation | p. 107 |
| Attributes for mixed-signal modeling | p. 108 |
| Mixed-signal simulation cycle | p. 114 |
| Analysis Domains | p. 116 |
| Supported domains | p. 116 |
| Small-signal and noise domain simulation | p. 118 |
| Summary | p. 124 |
| Selected RF Blocks in VHDL-AMS | p. 127 |
| Library Overview | p. 127 |
| Signal Sources | p. 128 |
| Independent sources | p. 128 |
| Modulated sources | p. 130 |
| Wobble generator | p. 133 |
| Pseudorandom binary source | p. 135 |
| Basic RF Building Blocks | p. 137 |
| Low-noise amplifier | p. 137 |
| Mixer | p. 142 |
| Charge pump | p. 146 |
| Analog VCO | p. 150 |
| Digital VCO | p. 153 |
| Filters | p. 157 |
| Switch | p. 163 |
| General n-bit A/D and D/A converter | p. 164 |
| Simple channel | p. 169 |
| Measurement and Observation Units | p. 174 |
| Peak detector | p. 174 |
| Frequency measurement unit | p. 175 |
| Power meter | p. 178 |
| Block Level Example of a Linear PLL | p. 183 |
| Macromodeling in VHDL-AMS | p. 191 |
| Introduction | p. 191 |
| General Methodology | p. 191 |
| Input and Output Stages | p. 194 |
| Input stages | p. 194 |
| Output stages | p. 197 |
| OpAmp Macromodel | p. 199 |
| Complex Example: Wlan Receiver | p. 203 |
| Introduction | p. 203 |
| Example Specification | p. 204 |
| Example Modeling | p. 207 |
| Example Calibration | p. 211 |
| Example Verification | p. 214 |
| Modeling of Analog Blocks in Verilog-A | p. 219 |
| Introduction | p. 219 |
| Writing Custom Behavioral Models | p. 220 |
| Verilog-A principles | p. 220 |
| LNA modeling example | p. 222 |
| Creating a Verilog-A model | p. 226 |
| Overview of the Cadence Model Library rfLib | p. 231 |
| Modeling and Simulation of a WLAN Receiver | p. 236 |
| WLAN receiver modeling using Cadence libraries | p. 237 |
| Simulation of the WLAN receiver | p. 240 |
| Characterization for Bottom-Up Verification | p. 247 |
| Concept of Characterization | p. 247 |
| RF Characteristics and Parameters | p. 248 |
| Application of Characterization | p. 252 |
| Example Characterization of an LNA | p. 254 |
| Characterization Environment | p. 258 |
| Characterization Using the OCEAN Script Language | p. 262 |
| Creation of the testbench schematic | p. 262 |
| Analysis settings and simulation | p. 263 |
| Combination and extension of the OCEAN scripts | p. 266 |
| Advanced Methods for Overall System Specification and Validation | p. 271 |
| Gap between System Level and Block Level Simulation | p. 271 |
| File Coupling of Simulators | p. 272 |
| Direct Cosimulation of System Level and Analog Simulators | p. 273 |
| Generated Black Box Models | p. 279 |
| References | p. 285 |
| Index | p. 287 |
| Table of Contents provided by Ingram. All Rights Reserved. |