Minimizing and Exploiting Leakage in VLSI Design

By: Nikhil Jayakumar, Suganth Paul, Rajesh Garg

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Hardcover | 3 December 2009

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244 Pages

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23.5 x 15.88 x 1.91

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Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.

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Non-Fiction Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computing & I.T.Graphical & Digital Media Applications Computer Science Computer Architecture & Logic Design

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Paperback

Published: 28th November 2014

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Introduction	p. 1
The Need for Low Power Design	p. 1
Leakage and Its Contribution to IC Power Consumption	p. 2
Summary	p. 5
References	p. 6
Leakage Reduction Techniques: Minimizing Leakage in Modem Day DSM Processes
Existing Leakage Minimization Approaches	p. 9
Leakage Minimization Approaches: An Overview	p. 9
Power Gating/MTCMOS	p. 9
Body Biasing/VTCMOS	p. 10
Input Vector Control	p. 11
Summary	p. 12
References	p. 13
Computing Leakage Current Distributions	p. 15
Overview	p. 15
Introduction	p. 15
Background	p. 17
Reduced Ordered Binary Decision Diagrams	p. 17
Algebraic Decision Diagrams	p. 19
The Intuition Behind Our Approach	p. 21
Related Previous Work	p. 22
Our Approach	p. 22
Exact Computation of the Leakages of All Vectors	p. 22
Approximate Computation of Leakages of All Vectors	p. 25
Experimental Results	p. 27
Summary	p. 30
References	p. 31
Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities	p. 33
Overview	p. 33
Introduction	p. 34
The Intuition Behind Our Approach	p. 35
Related Previous Work	p. 36
Our Approach	p. 38
Computing Signal Probabilities	p. 39
Finding the Best Leakage Candidate	p. 41
Finding Best Leakage State for Selected Gate	p. 41
Accepting Leakage States and Final MLV Determination	p. 43
Experimental Results	p. 45
Selecting Parameter Values for MLVC and MLVC-VAR	p. 45
Comparing MLVC with Existing Techniques	p. 46
Comparing MLVC-VAR with MLVC and RVA	p. 49
Summary	p. 52
References	p. 53
The HL Approach: A Low-Leakage ASIC Design Methodology	p. 55
Overview	p. 55
Philosophy of the HL Approach	p. 56
Related Previous Work	p. 56
The HL Approach	p. 57
Design Methodology	p. 59
Advantages and Disadvantages of the HL Approach	p. 60
Experimental Results	p. 62
Comparison of Placed and Routed Circuits	p. 63
Using Gate Length Biasing Instead of VT Change	p. 68
Leakage Reduction in Domino Logic	p. 71
Summary	p. 74
References	p. 76
Simultaneous Input Vector Control and Circuit Modification	p. 77
Overview	p. 77
Introduction	p. 77
The Intuition Behind Our Approach	p. 78
Related Previous Work	p. 79
Our Approach	p. 80
The Gate Replacement Algorithm	p. 82
Experimental Results	p. 84
Summary	p. 89
References	p. 90
Optimum Reverse Body Biasing for Leakage Minimization	p. 91
Overview	p. 91
Goal and Background	p. 92
Related Previous Work	p. 94
Leakage Monitoring/Self-Adjusting Scheme	p. 96
Leakage Current Monitoring Block (LCM)	p. 96
Digital Control Block	p. 98
Summary	p. 99
References	p. 99
Part I: Conclusions and Future Directions	p. 101
References	p. 104
Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design
Exploiting Leakage: Sub-threshold Circuit Design	p. 109
Overview	p. 109
Introduction	p. 109
The Opportunity	p. 111
Summary	p. 113
References	p. 113
Adaptive Body Biasing to Compensate for PVT Variations	p. 115
Overview	p. 115
Related Previous Work	p. 115
Preliminaries: PLAs	p. 116
PLA Design	p. 116
PLA Operation	p. 117
The Adaptive Body Biasing Solution	p. 118
Self-Adjusting Bulk-Bias Circuit	p. 120
Experimental Results	p. 122
Loop Gain of the Adaptive Body Biasing Loop	p. 124
Summary	p. 126
References	p. 127
Optimum VDD for Minimum Energy	p. 129
Overview	p. 129
Introduction	p. 129
Related Previous Work	p. 130
Preliminaries	p. 131
Operation of the PLA	p. 131
Some Definitions	p. 132
Experiments	p. 133
Energy Estimation for a Circuit of PLAs	p. 137
Summary	p. 141
References	p. 141
Reclaiming the Sub-threshold Speed Penalty Through Micropipelining	p. 143
Overview	p. 143
Our Approach	p. 144
Asynchronous Micropipelined NPLAs	p. 144
Synthesis of Micropipelined PLA Networks	p. 147
Circuit Details of PLAs and Stutter Blocks	p. 148
Experimental Results	p. 151
Optimum VDD for Micropipelined NPLAs	p. 152
Summary	p. 154
References	p. 155
Part II: Conclusions and Future Directions	p. 157
References	p. 159
Design of a Sub-threshold BFSK Transmitter IC
Design of the Chip	p. 163
Overview	p. 163
Test Vehicle	p. 163
BFSK Radio Transmitter Architecture	p. 164
System Architecture	p. 165
PLA Basics	p. 165
Network of PLA Operation	p. 166
Dynamic Compensation Circuit	p. 167
The Digital BFSK Modulator	p. 168
Digital to Analog Converter	p. 170
Common Source Amplifier	p. 171
Antenna	p. 172
Design Specifications	p. 172
Link Budget Analysis	p. 172
Summary	p. 174
References	p. 175
Implementation of the Chip	p. 177
Overview	p. 177
Design Flow	p. 177
HDL to Netlist Flow	p. 179
SPICE Verification of Dynamic Compensation	p. 180
DAC and Amplifier Design	p. 181
Special Considerations	p. 183
Testability and Redundancy	p. 183
Voltage Domains	p. 184
Standard Cell-Based BFSK Design	p. 185
IO Pad and ESD Diode Design	p. 185
Chip Integration and Pin-out	p. 186
Layout	p. 188
Summary of Verification Methodologies	p. 190
Summary	p. 190
References	p. 190
Experimental Results	p. 193
Overview	p. 193
Functional Verification	p. 193
Dynamic Compensation Circuit	p. 193
Operating Ranges	p. 196
Spectrum of Output Sinusoidal Signals	p. 197
Comparison with Standard Cells	p. 197
Summary	p. 199
Reference	p. 199
Summary and Future Work	p. 201
Conclusion	p. 203
Index	p. 205
Table of Contents provided by Ingram. All Rights Reserved.

Minimizing and Exploiting Leakage in VLSI Design

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Hardcover

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