| The Authors | p. xi |
| Dedications | p. xiii |
| Preface | p. xv |
| Introduction | p. xix |
| Contributing Authors in Order of Appearance | p. xxi |
| Analyzing and Driving Verification: An Executive's Guide | |
| The Verification Crisis | p. 3 |
| Automated Metric-Driven Processes | p. 13 |
| Introduction | p. 13 |
| The Process Model | p. 15 |
| The Automated Metric-Driven Process Model | p. 16 |
| Project Management Using Metric-Driven Data | p. 28 |
| What Are Metrics For? | p. 29 |
| Tactical and Strategic Metrics | p. 29 |
| Summary | p. 30 |
| Roles in a Verification Project | p. 31 |
| Introduction | p. 31 |
| The Executive | p. 31 |
| Marketing | p. 33 |
| Design Manager | p. 34 |
| Verification Manager | p. 34 |
| Verification Architect/Methodologist | p. 35 |
| Design/System Architect | p. 36 |
| Verification Engineer | p. 37 |
| Design Engineer | p. 38 |
| Regressions Coordinator | p. 39 |
| Debug Coordinator | p. 39 |
| Summary | p. 40 |
| Overview of a Verification Project | p. 41 |
| Introduction | p. 41 |
| Summary | p. 49 |
| Verification Technologies | p. 51 |
| Introduction | p. 51 |
| Metric-Driven Process Automation Tools | p. 52 |
| Modeling and Architectural Exploration | p. 58 |
| Assertion-Based Verification | p. 63 |
| Simulation-Based Verification | p. 70 |
| Mixed-Signal Verification | p. 73 |
| Acceleration/Emulation-Based Verification | p. 75 |
| Summary | p. 78 |
| Managing the Verification Process | |
| Verification Planning | p. 81 |
| Introduction | p. 81 |
| Chapter Overview | p. 83 |
| Verification Planning | p. 86 |
| Summary | p. 105 |
| Capturing Metrics | p. 107 |
| Introduction | p. 107 |
| The Universal Metrics Methodology | p. 109 |
| Regression Management | p. 113 |
| Introduction | p. 113 |
| Early Regression Management Tasks | p. 114 |
| Regression Management | p. 114 |
| Linking the Regression and Revision Management Systems | p. 115 |
| Bring-Up Regressions | p. 116 |
| Integration Regressions | p. 119 |
| Design Quality Regressions | p. 121 |
| Managing Regression Resources and Engineering Effectiveness | p. 122 |
| Regression-Centric Metrics | p. 123 |
| How Many Metrics Are Too Many? | p. 125 |
| Summary | p. 127 |
| Revision Control and Change Integration | p. 129 |
| Introduction | p. 129 |
| The Benefits of Revision Control | p. 131 |
| Metric-Driven Revision Control | p. 132 |
| Summary | p. 139 |
| Debug | p. 141 |
| Introduction | p. 141 |
| Debug Metrics | p. 144 |
| Summary | p. 153 |
| Executing the Verification Process | |
| Coverage Metrics | p. 157 |
| Introduction | p. 157 |
| Modeling and Architectural Verification | p. 163 |
| Introduction | p. 163 |
| How to Plan | p. 164 |
| Tracking to Closure | p. 165 |
| Reusing Architectural Verification Environments | p. 165 |
| Summary | p. 166 |
| Assertion-Based Verification | p. 167 |
| Introduction | p. 167 |
| How to Plan | p. 170 |
| Tracking to Closure | p. 175 |
| Opportunities for Reuse | p. 177 |
| Summary | p. 179 |
| Dynamic Simulation-Based Verification | p. 181 |
| Introduction | p. 181 |
| How to Plan | p. 183 |
| Taxonomy of Simulation-Based Verification | p. 187 |
| Tracking to Closure | p. 191 |
| Summary | p. 196 |
| System Verification | p. 197 |
| Introduction | p. 197 |
| Coverification Defined | p. 199 |
| Advancing SoC Verification | p. 201 |
| List of Challenges | p. 202 |
| ARM926 PrimeXsys Platform Design | p. 205 |
| Closing the Gap | p. 207 |
| DMA Diagnostic Program | p. 208 |
| Connecting the DMA Diagnostic to the Verification Environment | p. 212 |
| Connecting the Main() Function in C | p. 215 |
| Writing Stubs | p. 216 |
| Creating Sequences and Coverage | p. 217 |
| Conclusion | p. 219 |
| References | p. 220 |
| Mixed Analog and Digital Verification | p. 221 |
| Abstract | p. 222 |
| Introduction | p. 222 |
| Traditional Mixed-Signal Verification | p. 223 |
| Verification Planning | p. 225 |
| Analog Mixed-Signal Verification Kit | p. 229 |
| Conclusion | p. 233 |
| Reference | p. 234 |
| Design for Test | p. 235 |
| Introduction | p. 236 |
| Motivation | p. 238 |
| A Unified DFT Verification Methodology | p. 239 |
| Planning | p. 240 |
| Executing | p. 241 |
| Automating | p. 243 |
| Test Case | p. 245 |
| Benefits | p. 248 |
| Future Work | p. 249 |
| Conclusions | p. 249 |
| References | p. 250 |
| Case Studies and Commentaries | |
| Metric-Driven Design Verification: Why Is My Customer a Better Verification Engineer Than Me? | p. 255 |
| Abstract | p. 255 |
| Introduction | p. 256 |
| The Elusive Intended Functionality | p. 257 |
| The Ever-Shrinking Schedule | p. 265 |
| Writing a Metric-Driven Verification Plan | p. 270 |
| Implementing the Metric-Driven Verification Plan | p. 274 |
| Conclusion | p. 277 |
| Metric-Driven Methodology Speeds the Verification of a Complex Network Processor | p. 279 |
| The Task Looked to be Complex | p. 280 |
| Discovering Project Predictability | p. 281 |
| A Coverage-Driven Approach, a Metric-Driven Environment | p. 282 |
| A New Level of Confidence | p. 283 |
| Developing a Coverage-Driven SoC Methodology | p. 285 |
| Introduction | p. 285 |
| Verification Background | p. 286 |
| Current Verification Methodology | p. 289 |
| Coverage and Checking | p. 292 |
| Results and Futures | p. 293 |
| From Panic-Driven to Plan-Driven Verification Managing the Transition | p. 297 |
| Verification of a Next-Generation Single-Chip Analog TV and Digital TV ASIC | p. 303 |
| Abstract | p. 303 |
| Introduction | p. 304 |
| The Design | p. 305 |
| Verification Challenges | p. 306 |
| Addition of New Internal Buses | p. 307 |
| Module-Level Verification | p. 309 |
| Data Paths and Integration Verification | p. 309 |
| Management of Verification Process and Data | p. 309 |
| Key Enablers of the Solution | p. 310 |
| Results | p. 320 |
| Conclusions | p. 322 |
| Future Work | p. 322 |
| Management IP: New Frontier Providing Value Enterprise-Wide | p. 325 |
| Adelante VD3204x Core, Subsystem, and SoC Verification | p. 329 |
| Abstract | p. 330 |
| Introduction | p. 330 |
| Project Background | p. 331 |
| Verification Decisions | p. 333 |
| DSP Core Verification | p. 335 |
| DSP Subsystem Verification | p. 338 |
| SoC-Level Verification | p. 341 |
| Results and Future Work | p. 342 |
| SystemC-based Virtual SoC: An Integrated System-Level and Block-Level Verification Approach from Simulation to Coemulation | p. 345 |
| Abstract | p. 346 |
| Introduction: Verification and Validation Challenges | p. 347 |
| Virtual SoC TLM Platform | p. 348 |
| Functional Verification: Cosimulation TLM and RTL | p. 350 |
| Validation: Coemulation TLM-Palladium | p. 352 |
| Conclusion and Future Developments | p. 353 |
| Is Your System-Level Project Benefiting from Collaboration or Headed to Chaos? | p. 355 |
| Index | p. 359 |
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